SCLD Substitute Card Description ------------------------------------ Original Rev. 3-JUNE-2007 Current Rev. 14-JUNE-2007 ***************************** ***** ***** ***** DRAFT Version ***** ***** ***** ***************************** The intent is to make a SCLD Substitute Card (SCLD_Sub) that has just enough of the functionality of a real SCLD card to run one crate of ADF-2 cards in their LArTPC application. This note is a description of the SCLD_Sub card. The SCLD_Sub is needed so that we can operate ADF-2 cards both at T962 and at MSU. 1. There is no option but to use one of the spare 60.6905 MHz VCXO as the basic timing signal. 53.104 MHz i.e. right about the middle of the normal range x 8/7 is 60.6903 MHz. 2. Thus divide the 60.6903 MHz by 8 to get the basic 7.586 MHz "Tick Clock". This is a straight forward divide by 8. This is the same thing as 53.104 MHz divided by 7. 3. Begin_of_Turn Marker I know that we need this for the LArTPC application. It does not need to happen every 159 cycles of the Tick Clk as it does in the D-Zero application for synchronization with the Tevatron. For the LArTPC application it will just be asserted once every 128 or 256 cycles of the Tick Clock. 4. Live_BX Marker I do not think that we need the Live_BX Marker for the LArTPC application, but it should be driven to a defined level. It would be nice to tie it to something that toggles at some rate (BX divided by N). 5. From the External Trigger input we need to generate the Collect_Monitor_Data signal after a programmable delay. We also need to make this function enabled/disabled based on the Crate_to_SCLD_Signal_0. This is need to control when triggers are allowed to happen, i.e. not during the initial full turn to fill of the circular buffers. 6. Crate_to_SCLD_Signal_1 is used to force the immediate generation of the Save_Monitor_Data signal. Although it is not used right now in the DAQ-96 system, this should probably be included in the SCLD_Sub. 7. It also makes sense to include the trigger signal optical fiber to copper converter in the SCLD_Sub. Thus we need to have both a BNC TTL External Trigger Input and an optical fiber External Trigger Input on the SCLD_Sub. 8. The SCLD to Maestro ADF-2 card cable pinout is the following: ADF-2 ADF-2 Diff Signal Name P0 Pin Direction Signal Description Polar ----------------- ------ --------- -------------------------- ----- CRATE_TO_SCLD_0_P A1 ADF->SCLD Crate to SCLD Signal #0 Dirct CRATE_TO_SCLD_0_N B1 ADF->SCLD Crate to SCLD Signal #0 Compl GROUND C1 SCL_LIVE_BX_P D1 SCLD->ADF Live Beam Crossing Dirct SCL_LIVE_BX_N E1 SCLD->ADF Live Beam Crossing Compl SCL_INIT_P A2 SCLD->ADF SCL Initialization Request Dirct SCL_INIT_N B2 SCLD->ADF SCL Initialization Request Compl GROUND C2 CRATE_TO_SCLD_1_P D2 ADF->SCLD Crate to SCLD Signal #1 Dirct CRATE_TO_SCLD_1_N E2 ADF->SCLD Crate to SCLD Signal #1 Compl SCL_BX_CLOCK_P A3 SCLD->ADF Beam Crossing (Tick) Clock Dirct SCL_BX_CLOCK_N B3 SCLD->ADF Beam Crossing (Tick) Clock Compl GROUND C3 SCL_BEGIN_TURN_P D3 SCLD->ADF Begin of Turn Marker Dirct SCL_BEGIN_TURN_N E3 SCLD->ADF Begin of Turn Marker Compl SAVE_MONIT_DATA_P A4 SCLD->ADF Save Monitoring Data Dirct SAVE_MONIT_DATA_N B4 SCLD->ADF Save Monitoring Data Compl GROUND C4 SCLD_SPARE_P D4 SCLD->ADF Spare Signal Dirct SCLD_SPARE_N E4 SCLD->ADF Spare Signal Compl 9. Recall the pinout of the SCLD to Maestro ADF-2 Cable Looking at the back of the ATC card, i.e. looking from the back of the crate, the AMP LVDS plugs in with its white side to the right. Looking into the hard metric connector on the SCLD_Sub, i.e. looking from where the cable plugs in, the white side of the AMP LVDS cable is on the right. Looking at the back side of the hard metric connector, or looking at the face of the connector on SCLD_Sub end of the cable, the layout of the pins is: A1 B1 C1 D1 E1 A2 B2 C2 D2 E2 A3 B3 C3 D3 E3 A4 B4 C4 D4 E4 10. Recall the timing of the control signals wrt the Tick Clock edges On the real SCLD ALL signals sent from the SCLD to the Maestro ADF-2 card are updated (in I/O Block latches) on the positive edges of the 53 MHz clock. The "control" signals, e.g. Begin of Turn, change states 2 cycles of the 53 MHz clock after the Tick Clocks positive edge. 11. Recall the LVDS levels The typical LVDS differential signal level is 350 mV. This comes from a 3.5 mA current source in the transmitter and the 100 Ohm differential terminator at the receiver. The typical common mode voltage is 1.2 Volts. The receiver wants the differential input to be between 100 mV and 600 mV with the common mode between 0.5 Volts and 2.0 Volts. 12. To make some "LVDS like" outputs on the existing kludge module we can use 510 Ohm series resistors with 2k to ground. The only LVDS signals that we need to receive are the slowly changing CRATE_TO_SCLD_0 which we can do with a 339. 13. Version #1 of the SCLD_Sub was made so that it directly drives the BX_Clock, Begin_of_Turn, and Live_BX signals onto the backplane using 74ls38 open collector drivers. Thus it can control only one crate of ADF-2 cards but it does not need LVDS drivers and you do not need a Maestro type ADF-2 card in the crate.