LArTPC DAQ 96 Hardware Routines ------------------------------------- Original Rev. 27-DEC-2006 Current Rev. 29-DEC-2006 The purpose of this file is to describe some of the low level routines that actually manipulate the control registers in the ADF-2 cards. The sections of this document are: ADF-2 Hardware Control Routines Setup ADF-2 Card Input Control Registers Start the Address Generators Read the Address Generator Stop Address Enable / Disable the External NIM Trigger Address of the Raw ADC Data Circular Buffers GUI Command File Routines Configure all cards in the DAQ 96 System Initialize all cards in the DAQ 96 System Run Find_DAC on all cards in the DAQ 96 System ADF-2 Hardware Control Routines =============================== Setup the ADF-2 Card Input Control Registers -------------------------------------------- For the LArTPC DAQ 96 application the ADF-2 Card Input Control Registers must be setup for recording the Raw ADC Data. This is done in the following steps. Note that we will always setup all ADF-2 Cards that are in the current DAQ 96 System configuration (as given by the list List_of_DAQ_96_ADF_2_Cards) even though in a given run we may not be reading out all of these cards. Setup the Input Control Registers for all 16 channels in each Data Path FPGAs on all of the ADF-2 cards in the DAQ 96 System so that: Stop Comparator is set to ADC full scale counts = 1023 i.e. set Bits 7:0 = $FF Set zero ADC data delay, i.e. set bits 11:8 all Low Select ADC data to go to the Filter, i.e. set bit #12 Low Channel's Raw ADC Mem Block Write Enable to follow the Address Generator Global Write Enable, i.e. set Bit #14 Low Loop over all of the ADF2_Card_Numbers that are in the list List_of_DAQ_96_ADF_2_Cards. For all 16 channels in each of the Data Path FPGAs on each ADF-2 card do the following: # Setup Ch 0 EM Input Control Register Rio_Write( MasterNum = 0, SlaveNum = 0, SlotNum = "ADF2_Card_Number + Slot_Num_of_ADF2_Card_Num_Zero", ChipNum = 0, RegAddr = 0x302, DataOut = 0x00ff ) # Setup Ch 0 HD Input Control Register Rio_Write( MasterNum = 0, SlaveNum = 0, SlotNum = "ADF2_Card_Number + Slot_Num_of_ADF2_Card_Num_Zero", ChipNum = 0, RegAddr = 0x303, DataOut = 0x00ff ) Now go through these steps again for Data Path FPGA #1, i.e. ChipNum = 1. EM Input Control Register register addresses: TT=0 TT=1 TT=2 TT=3 TT=4 TT=5 TT=6 TT=7 ----- ----- ----- ----- ----- ----- ----- ----- $302 $2302 $4302 $6302 $8302 $A302 $C302 $E302 HD Input Control Register register addresses: TT=0 TT=1 TT=2 TT=3 TT=4 TT=5 TT=6 TT=7 ----- ----- ----- ----- ----- ----- ----- ----- $303 $2303 $4303 $6303 $8303 $A303 $C303 $E303 Start the Address Generators ---------------------------- The following are the steps to start the Address Generators for the Raw ADC Mem Blks. Set the Highest Address to 2046. Then start the Address Generator running with: enable multi turn running enable the Global Write Enable signal to be asserted enable the Save Monitor Data signal to stop the Address Generators On each ADF-2 Card we must start up the Address Generator in both Data Path FLGAs. We will always startup the Address Generators on all of the ADF-2 cards that are currently defined as being in the DAQ 96 System even though for a given run we may not be reading out all of the ADF-2 cards that are in the current system setup. Loop over all of the ADF2_Card_Numbers that are in the list List_of_DAQ_96_ADF_2_Cards. For each ADF-2 card do the following: Rio_Write( MasterNum = 0, SlaveNum = 0, SlotNum = "ADF2_Card_Number + Slot_Num_of_ADF2_Card_Num_Zero", ChipNum = 0, RegAddr = 513, DataOut = 2046 ) Rio_Write( MasterNum = 0, SlaveNum = 0, SlotNum = "ADF2_Card_Number + Slot_Num_of_ADF2_Card_Num_Zero", ChipNum = 0, RegAddr = 512, DataOut = 0x000e ) Rio_Write( MasterNum = 0, SlaveNum = 0, SlotNum = "ADF2_Card_Number + Slot_Num_of_ADF2_Card_Num_Zero", ChipNum = 0, RegAddr = 512, DataOut = 0x000f ) Rio_Write( MasterNum = 0, SlaveNum = 0, SlotNum = "ADF2_Card_Number + Slot_Num_of_ADF2_Card_Num_Zero", ChipNum = 0, RegAddr = 512, DataOut = 0x000e ) Now go through these steps again for Data Path FPGA #1, i.e. ChipNum = 1. Read the Address Generator Stop Address --------------------------------------- We need to read the address at which the Address Generators stopped in each Data Path FPGA. Note that, unlike in the D-Zero operation, in the DAQ 96 operation the Address Generators on the different Data Path FPGAs and on the different ADF-2 cards will typically be at stop at different addresses. This is because, although the Address Generators always start synchronous with the Begin of Turn Marker, in the DAQ 96 application their cycle length, i.e. 2048, is not an integral multiple of the turn length (as it is in the D-Zero application). So for each ADF-2 card read: ChipNum = 0, RegAddr = 514, and ChipNum = 1, RegAddr = 514 to get the two Address Generator stopping addresses for that ADF-2 card. Enable / Disable the External NIM Trigger ----------------------------------------- The External NIM Trigger is ENABLED by telling the Maestro ADF-2 card, i.e. ADF-2 Card Number #0, to send an asserted ADF_Crate_to_SCLD_Signal_0 signal to the SCLD card. Do this by writing to the Board Control PAL Register Address 1. Rio_Write( MasterNum = 0, SlaveNum = 0, SlotNum = "Slot_Num_of_ADF2_Card_Num_Zero", ChipNum = 0, RegAddr = 1, DataOut = 0xff50 ) The External NIM Trigger is DISABLED by telling the Maestro ADF-2 card, i.e. ADF-2 Card Number #0, to send a NOT asserted ADF_Crate_to_SCLD_Signal_0 signal to the SCLD card. Do this by writing to the Board Control PAL Register Address 1. Rio_Write( MasterNum = 0, SlaveNum = 0, SlotNum = "Slot_Num_of_ADF2_Card_Num_Zero", ChipNum = 0, RegAddr = 1, DataOut = 0xff40 ) Address of the Raw ADC Data Circular Buffers -------------------------------------------- For the DAQ 96 applications the Raw ADC Data Circular Buffer had to be increased in size from the 1024 locations as used in the D-Zero application to 2048 locations. Making this modification required removing the Et Lookup Memory and the Final Output Data Circular Buffer from the D-Zero firmware. In the LArTPC firmware the Raw ADC Data Circular Buffer has been moved to the address block that holds the Et Lookup Memory in the D-Zero application. This was done so that the standard D-Zero ADF-2 Card Initialize routine could still be used with the DAQ 96 firmware. The starting addresses of the 2048 location long Raw ADC Data Circular Buffers in the LArTPC firmware are listed near the end of the document: daq_96_definition.txt GUI Command File Routines ========================= Configure all cards in the DAQ 96 System ----------------------------------------- Initialize all cards in the DAQ 96 System ----------------------------------------- Run Find_DAC on all cards in the DAQ 96 System ----------------------------------------- All ADF-2 card channels will have their pedestal set to 400 ADC counts. Loop over all of the ADF2_Card_Numbers that are in the list List_of_DAQ_96_ADF_2_Cards. For all 32 channels on each ADF-2 card do the following: Find_Dac( MasterNum = 0, SlaveNum = 0, SlotNum = "ADF2_Card_Number + Slot_Num_of_ADF2_Card_Num_Zero", TtType = 0, RelEta = 0, RelPhi = 0, AdcValue = 400, DumpToFile = 0 ) In the above, the arguments: TtType, RelEta, and RelPhi are manipulated to make the loop over all 32 channels that are on a given ADF-2 card.