LArTPC DAQ 96 Trigger Input ------------------------------- Original Rev. 31-OCT-2006 Current Rev. 11-DEC-2006 The purpose of this file is to describe the general process via which the DAQ system for the LArTPC test cryostat is triggered. This file does not describe the actual generation of the trigger signal (via scintillator and PMT tubes and NIM logic I assume) but rather this file describes how this trigger signal is used in the DAQ system. The current basic philosophy for building the SCLD and ADF-2 part of the LArTPC test DAQ system is to keep the operation of these cards as much as possible the same as how they are used at D-Zero. The alternative is to make all new firmware and possibly some small hardware modifications to make a setup that is specifically designed for the LArTPC test cryostat. That may be the way to go in the long run, but for now the plan is to keep things as much as possible like the D-Zero operation until we get something running and learn for certain what is ideally needed for LArTPC. Basic Assumptions: ------------------ 1. I will assume that the DAQ system is handed a NIM level External Trigger Signal that lasts for longer than 132 nsec (pick 150 nsec as the target). 2. The ADF-2 cards will run in their normal "Monitor Data" collection loop, i.e. the Address Generator is running and ADC data is being written into the Raw ADC Monitor Data Block circular buffers. 3. As in the D-Zero application, the ADF-2 cards just keep recording Raw ADC data until the Address Generator is stopped by the "Save Monitor Data" signal. The NIM external trigger signal will be processed into the "Save Monitor Data" signal on the SCLD card. For part of this processing the SCLD card uses the same logic as it uses in the D-Zero application to processes the L1_Acpt plus L1_Qual_7 into the Save Monitor Data signal. For LArTPC operation the processing of the external trigger signal will have the following steps: 1. Receive the NIM external trigger signal and convert it to a 3.3V CMOS logic signal and send it to the SCLD FPGA. This hardware processing will be done on a small perf board that plugs into the DeBug connector on the SCLD card. 2. Once the external trigger signal is in the FPGA (received by an I/O Block FD) then sync it up with the 53 MHz and then the 132 nsec clocks. 3. The external trigger signal must now be delayed before it is actually used to cause the Save_Monitor_Data signal. You need this delay because the external trigger signal will come from the PMTs and NIM electronics almost immediately after the muon goes through the LArTPC detector but we must wait for the electrons to drift into the grids and be readout before stopping the writing of ADC data in the ADF-2 card circular buffers. 4. To get started we will make the delay of the external trigger signal as a number of 132 nsec steps. This done with a 16 bit counter. This counter starts when the external trigger signal arrives and it increments once every 132 nsec. The output of this comparator goes to a 16 bit comparator with bits numbered MSBit:LSBit 15:0. The reference value for this comparator comes, in part, from an 8 key DIP switch mounted on the perf board above the DeBug connector. The 8 keys on this DIP switch control bits 11:4 of the reference value to the comparator. The comparator reference value bits 15:12 and 3:0 are hardwired LOW. After being started by the external trigger signal, once the counter has reached the comparator's reference value then a delayed trigger signals is sent on to the rest of the circuit. 5. This delayed trigger signal goes to the Generate Save Monitor Data section of the SCLD FPGA design (instead of the L1_Acpt + L1_Qual_7 signals used in the D-Zero application). 6. At this point the processing of the delayed trigger signal into the Save Monitor Data signal looks the same as the D-Zero setup, i.e. the the "Crate_0_ADF_Sig_0" must be asserted to allow the trigger signal to initiate a Save_Monitor_Data signal or else the "Crate_0_ADF _Sig_1" can be used to initiate an immediate Save_Monitor_Data. 7. The Save_Monitor_Data signal to the ADF-2 Crate is 132 nsec long and is correctly aligned with the BX_Clock using the same logic that is used in the D-Zero setup. 8. At this point the Save Monitor Data signal leaves the SCLD card and travels to the ADF Crate on a LVDS cable. Once this signal is in the ADF Crate it can stop the writing of ADC data into the circular buffers in the ADF-2 cards. Control of the External Trigger Signal Delay -------------------------------------------- Time Interval Key Number Comparator Number of Controlled on DIP SW Reference Value Bit 132 nsec Ticks by this Key ---------- ------------------- -------------- ------------- 1 bit #4 16 2.1 usec 2 bit #5 32 4.2 usec 3 bit #6 64 8.4 usec 4 bit #7 128 16.9 usec 5 bit #8 256 33.7 usec 6 bit #9 512 67.5 usec 7 bit #10 1024 135.0 usec 8 bit #11 2048 270.0 usec With a key set OPEN it means that the total delay time includes the time interval controlled by that key. For example with just keys #7 and #8 set OPEN, and all the other keys CLOSED, then the total delay of the external trigger signal would be 405 usec before the Save Monitor Data signal is generated and the ADC circular buffers are stopped.