LArTPC Test Cryostat DAQ System ------------------------------------- Original Rev. 27-JAN-2006 Current Rev. 1-FEB-2006 This note describes the construction of a DAQ system for use with the LArTPC test cryostat at Fermilab, e.g. for use with the long drift test cryostat. This note has 5 sections which are: Design Intent Description of the Hardware Components Description of the DAQ Computer and Its Software Description of Other Components Points for Discussion Design Intent ------------- The focus of this design is to quickly provide at low cost a DAQ system that can be used with the LArTPC long drift test cryostat at Fermilab. To quickly implement this DAQ system a number of components have been borrowed from other system, mostly from D-Zero. Where design options are available, the choices made were to minimize the risk that a LArTPC test might fail because of some property of this DAQ system. It is not the intent of this DAQ system to be a prototype for the DAQ system that would be needed for a full scale LArTPC experiment which would involve some hundreds of thousands of channels. The design of this test cryostat DAQ system does not include complicated event topology based self triggering or readout data sparsification capabilities. This DAQ system is not designed for high event rate which is not thought to be necessary for the collection of muon events passing through the test cryostat. Description of the Hardware Components -------------------------------------- Preamp Enclosure The Preamps and other front-end components are mounted in an enclosure that is bolted directly onto the test cryostat. The enclosure covers the port in the cryostat that brings out the detector signals. The intent of this is three fold: Minimize the chance of noise pickup on the signals cables running from this port to the Preamps. Minimize the length and thus the capacitance and thus the added noise from this cable run. Insure that the ground reference of the Preamps is the same at the cryostat. The Preamp Enclosure is made from a standard NEMA electrical box by drilling and machining the required holes. This inexpensive commercial steel box provides a nice outer layer of magnetic and electrostatic shielding. Preamp Power Supplies These are standard commercial linear power supplies making +8 Volts and -6 Volts. These same supply Voltages are used for both the Preamps and the Filter - Postamp. About 0.5 Watts of power is needed per channel by the electronics in the Preamp Enclosure. For a modest system of a few hundred channels this requirement is easy to meet with readily available inexpensive linear supplies. The Preamp Power Supplies are mounted in their own enclosure which is bolted to the Preamp Enclosure. This Preamp Power Supply Enclosure is also a commercial NEMA steel electrical box with the appropriate holes machined in it for cables and ventilation. Preamp Power Isolation Transformer The purpose of the isolation transformer in the AC power line to the Preamp Power Supplies is to reduce the movement of the Preamp Ground caused by the standard un-balanced 120V AC outlet power. A second purpose of this isolation transformer is to help break the AC ground loop that forms because of the AC input to DC output capacitive coupling in the Preamp Power Supplies. This isolation transformer can be mounted some convenient distance from the cryostat. At the required power level this is not an expensive item. We have one available at MSU that can be used if needed. Preamps The intent is to use D-Zero Dual FET Preamps that were designed for Run II. A number of species of these Preamps were made. The various species differ only in the value of 3 passive components. Each species was designed to compensate for a given range of detector capacitance. Species "A" was designed for the lowest capacitance EM detector elements at D-Zero and most closely meets the needs of the LArTPC tests. Any species of these Preamps could be used in the LArTPC tests by changing a couple of passive components on the Preamp hybrid. There may be some benefit in changing up to 4 of the passive components to achieve the best Preamp performance with the LArTPC level and speed signals. The design of the D-Zero Dual FET Preamp includes two basic stages. First there is the standard "charge sensitive" input stage. This is followed by a differential output driver stage which has some additional voltage gain. There is a lot of information available on the web about these Preamps. A good place to start is: www-d0.fnal.gov/hardware/cal/preamp/ The following is a brief description of the passive components that we may want to change on these Preamps to optimize their performance with LArTPC signals. I have verified that these changes can be made and that they are not difficult to make. C3 This is the input stage feedback capacitor. Change it from 5 pFd to 2 pFd i.e. change the signal level at the output of the Preamp's input stage from 0.2 mV per femto-coul to 0.5 mV. R6 This is the input stage feedback resistor. Change it from 3 meg Ohm to 10 or 20 meg Ohm. That is lower the high pass cutoff frequency to match the slower LArTPC signals. R36 This is a compensation resistor used with large value detector capacitances. Set it to zero Ohms. In the A species Preamps this resistor is zero Ohms. If an other species is used then jumper out this resistor. R12 This is the gain setting resistor at the input to the differential output driver stage. Change it from 3.33k Ohm to 1k Ohm to boost the voltage gain of the output stage from 3 to 10. If easier, the existing R12 can just be paralleled with a 1.43 k Ohm resistor. C6 This is the input coupling capacitor to the differential output driver stage. Change this from 0.15 uFd to something in the range of 27 nFd to raise the low frequency cutoff frequency of the output stage. Don't pass signals at a lower frequency than the actual Physics signal that comes out of the detector. Preamp Motherboards The Preamp Motherboards (PMBs) will need to be a new design because nothing that we currently have is appropriate for use with the LArTPC DAQ system. The PMB serves a number of functions which will be described separately below. The design of this circuit board needs to enforce good layout for low level signals but otherwise is not complicated. The design of this circuit board can be guided by the design of the Preamp Motherboards used in the D-Zero DAQ system. The intent is that all detector channels that are serviced by a given PMB will be from the same wire plane in the LArTPC detector. Each PMB will distribute the same wire plane Bias Voltage to all of its channels. Thus a minimum system requires 3 PMBs - one for each of the 3 wire planes. The tentative design of the PMB calls for 32 channels per card. This number of Preamp hybrids should be easy to accommodate on a modest size motherboard and is less than the 48 channels on the D-Zero Preamp Motherboards. 32 channels on a PMB matches the channel count on the ADF-2 card which will be used for the ADC and digital circular buffer in this DAQ system. The tentative design calls for two sets of output connectors on the PMB. One set of connectors would be use if the 32 Preamp channels on the PMB are connected to the 32 channels on a single ADF-2 card. When using all 32 channels on the ADF-2 card it has enough memory to provide each channel with a 2048 long circular buffer memory. The other set of output connectors on the PMB card connects the Preamp channels with just every other channel on the ADF-2 card. In this case, two ADF-2 cards are needed to service the 32 Preamp channels on a single PMB, but the ADF-2 can provide each channel with a 4096 long circular buffer memory. The cable that runs from the output connectors on the PMB to the ADF-2 cards is a 3M Pleated Foil Cable. Each cable will carry the signals for either 8 or 16 preamplifier channels. The examples of this Pleated Foil Cable that I used in the Preamp tests are 15 feet long. That allows the ADF-2 cards to be located at some distance from the Preamp Enclosure. If we want Physics signals in the LArTPC tests to have an amplitude of 50 ADC counts or so then the signal level at the output of the D-Zero Dual FET Preamp is not appropriate for directly connection to the ADF-2 card's analog input. More Voltage gain and some filtering in frequency space are needed before the Preamp output signal is sent to the ADF-2 card. This addition gain and filtering are provided by the Filter - Postamp circuits on the PMB card. The 32 channels of Filter - Postamp are built right on the PMB card, i.e. they are not hybrid circuits that plug into the PMB as the Preamps do. Once the filter and gain parameters are established then the design of the Filter - Postamp is straight forward. The tentative design calls for using fully differential amplifiers as was done in the test setup for the preamplifier tests (and as I have used in other designs). Keeping this part of the circuit differential will make it match the differential output signal from the Preamp and the differential input connection to the ADF-2 cards. The PMB provides the distribution and filtering of the low Voltage DC supplies that power both the Preamps and the Filter - Postamps. Understanding how to layout this power distribution was gained from studying the design of the D-Zero Preamp Motherboards. The requirement is to make these power buses low noise and very stiff over the frequency range of the signals that are handled on the PMB. The Preamp hybrids themselves contain a final stage of power supply filtering. Another important function contained on the PMB is the wire plane Bias Voltage supply filter and distribution network. Part of this network is the coupling capacitors that allow the DC Bias Voltage to be present on the detector wires but block it from appearing at the input of the Preamps. The final filter for the wire plane Bias Voltage on the PMB is a simple RC filter. Because of the low current required by the detector wires it is possible to use such a simple filter and still achieve good attenuation of Bias Voltage noise in the frequency range of the detector signals. An important specification of the PMB will be the maximum Bias Voltage that it needs to be able to handle. The leakage and noise characteristics of the capacitors used in this filter will be important factors in achieving the required low noise levels. The return to ground of the noise current will be an important layout issue. The wire plane Bias Voltage distribution network includes a 10 meg Ohm resistor that feeds each channel. These clearly need to be low excess noise components (I assume thin metal film) and in the required Voltage rating they may only be available as through hole components. The wire plane Bias Voltage DC blocking capacitors are another critical passive component. Excess dielectric noise in these capacitors appears as input signal to the Preamps. These capacitors with the correct dielectric and Voltage rating may only be available in through hole device packages. The PMB will include a set of distribution nets for test pulse signals. To verify that adjacent channels are not coupled to each other it is necessary to have at least 2 nets for the distribution of test pulses. Having 4 nets gives some added benefit. The test pulses are connected to the Preamp inputs by high value resistors (i.e. the correct way for low noise current signals and not by small value capacitors as is often seen in other designs). To insure the lowest possible noise level the intent is to be able to unplug the source of the test pulses from the PMB for normal operation. The PMB will include clips for mounting metal shields over the low level signal portion of the circuit board. This is the inner layer of shielding and is most effective if it is at exactly the same ground potential as is used by the Preamp circuits. VME Crate and ADF-2 Cards The ADF-2 cards which provide the 10 bit ADCs and circular buffer memories for this DAQ system are mounted in a 6U VME crate. This crate needs to have the modern VME-64X type backplane. The ADF-2 cards requires the extra "D" and "Z" column bused signals in the VME-64X backplane. The crate that we have worked with is a standard commercial unit that is manufactured by Wiener in Germany. This crate includes power supplies and cooling fan. Wiener supplies lots of crates to CERN and for some of the new systems at Fermi (e.g. the new Tevatron BLM system). These crates are nicely made and expensive - order of $10k. My assumption is that we could use the spare crate for the D-Zero Run IIB L1 Cal Trig system to get started with the LArTPC test cryostat DAQ system. My assumption is that we can use some of the spare ADF-2 cards that are also part of the D-Zero Run IIB L1 Cal Trig system. This trigger system uses 80 of the ADF-2 cards and there are 20 spare cards for this system. I would not expect a significant number of failures of these cards during normal operation of this trigger system. Description of the DAQ Computer and Its Software ------------------------------------------------ The DAQ computer is a normal PC running the Fermilab version of Linux. The intent is that this is a 100% vanilla Fermi Linux machine so there is no problem with Computer Division security regulations or with having this machine maintained by Fermilab. Nothing special is needed on this machine to run the DAQ software. The interface between this machine and the VME crate is a standard commercial product from Bit-3 (SBC). This type of PCI to VME interface is used in many other systems at Fermilab and many people are familiar with it. The intent is to use the fiber optic version of this Bit-3 interface. The benefit of this is that it completely eliminates the grounding and power source issues for the computer and it allows the computer to be located at a considerable distance from the test cryostat. We have a PC and Bit-3 interface that can be used for the development of the LArTPC test cryostat DAQ system. The software for the DAQ system is "leveraged" from the software that is used to setup and monitor the Run IIB L1 Cal Trig system at D-Zero. Because of the modular design of this D-Zero software it will not be a big problem to modify it for use with the LArTPC test cryostat DAQ system. The following points describe this software and give an idea of how it would be used. - The intent is that this software would be supportable for some time but it is not meant to be greatly expandable. It is not a prototype of the DAQ software for a full size LArTPC experiment. This DAQ software is designed for easy operation with the test cryostat. - It is written in the modern standard Fermilab way using c++ and Python. - This DAQ software only provides for the recording of the event data and for simple viewing of single events. There is no intent to provide any type of data analysis in this package. - The strong intent is that this DAQ software be easy to run and that the event data recorded by it be easy to access by other people (including "non computer expert" people). - There is a single "configuration file" that tells the system which channels are to be readout and where the root of the directory tree is that will be used to hold the event data. This is a simple ascii file with clear English statements in it, e.g. "readout slot #5 channels 8:15". The intent is that a non expert can edit this file when necessary. - When starting a new Run the DAQ software creates a new directory (under the root specified in the configuration file) to hold the events from this Run. This directory is given an easy to understand name that includes a Run Number and the date and time that the Run was started. - When starting a new Run the operator is asked a few simple questions: Do you want this Run to go on for a fixed number of events, or for a fixed length of time, or until you manually end it ? No matter how you answer this question you can always manually end the Run. Do you wan the events collected by this run to be in response to the trigger from the scintillator detectors or do you just want the DAQ system to generate random asynchronous triggers by itself ? If you are just studying the noise then random triggers may be the best way to collect your data. Do you want the DAQ system to enforce a minimum length of time between events ? This is a simple way to enforce a kind of "pre-scale" with the hardware that is used in this DAQ system. - The data from each event in this Run is recorded in its own file in the directory for this Run. Each of these files has a name that includes and Event Number and a time stamp. - The event data in each of these files is simple straight forward ascii decimal data. The data from each channel is identified by a line that gives the slot number and channel number of the ADF-2 card that this data came from. This line also contains the address at which the circular buffer memory was stopped. This line is followed by data for this channel, i.e. 2048 decimal 4 digit numbers in the range 0:1023. - The intent is to make this event data very easy to access. The system could be made to run faster with a more compact data format but there is no intent (or need) to design this system to run faster than a couple of Hz. - There is no need to make this DAQ system faster than the rate of muons through the section of the test cryostat that is being studied. - Coordination of the DAQ PC with the hardware is simple. For example when recording events collected in response to the scintillator trigger the DAQ PC goes through the following loop. Start all ADF-2 channels recording data in their circular memory buffers. Wait long enough so that all circular buffers have recorded at least one full turn of new data. Enable the ADF-2 cards to immediately stop the writing of new data into their circular buffer memories when the external scintillator trigger signal is received. Poll the VME crate at 100 Hz (or something) to see if the circular buffer memories are still recording new data. When they stop recording new data then open a new file for this event and write into that file the data from all of the ADF-2 channels that are listed in the configuration file. After all the data from this event has been recorded then close the file and, if you have been told to, go to sleep for "N" msec of "prescale time" before returning to the top of this loop. - A rough version of this DAQ software already exists. It was used to collect that data that was used to study the D-Zero Dual FET Preamps operating with LArTPC size input signals. Description of Other Components ------------------------------- Trigger Signal from Scintillator Setting up the scintillator trigger for detecting muons going through the test cryostat is not included in this DAQ system. Coordination with the people setting up these scintillator detectors and NIM logic will be needed. When the DAQ system is enabled to record events in response to the scintillator trigger, writing of data into the circular buffer memories stops as soon as the trigger signal is received. Thus if the operators want the buffers to hold some data past the time that the muon passes through the LArTPC test cryostat, then the trigger signal to the DAQ system needs to be delayed by this amount in the NIM logic. Trigger Signal Receiver Card The trigger signal from the scintillator detectors is received by a card in the VME crate. This card is a hand made "perf board kludge card" that contains just a few gates. The scintillator trigger signal is received and placed onto a bused line that runs to all slots in the crate. A similar "one of a kind" card was made and used during the development of the ADF-2 equipment for the D-Zero Run IIB L1 Cal Trig. Wire Plane Bias Voltage Supplies Low noise supplies for the wire plane Bias Voltage need to be found. I assume that these could just be 3 Droege supplies. The Preamp Enclosure needs to include a filter on these supply Voltages right as they enter the enclosure. Test Pulser A very simple test pulser is needed to inject a signal into the test pulse distribution nets on the PMBs. To keep things simple and to keep the focus on the low noise operation of this DAQ system there is no plan for a fancy test pulser. The plan is to use the existing "hand pulser" and to move its signal from one test pulse distribution network to the next going through the 3 PMBs. Going through the signals in this way will allow verification that all channels are working and that they are responding with the same level of ADC output. Points for Discussion --------------------- How many channels are needed ? My preference is to start with 96 channels, i.e. 3 PMB cards and make that work (i.e. see real signals) before expanding the channel count. What is the maximum wire plane Bias Voltage that will be required ? This affects the design of the PMB and the Bias Voltage components that are used on it. I hope this does not go over a few hundred Volts. Coordination is needed with the people who will setup the scintillator detector trigger. Besides the trigger signal timing issue there is the question of how wide to make the scintillator detectors themselves ? That is, how narrow of a drift range does one need to constrain the muon to passing through ? The answer to this involves how fast do you want to sample the ADCs in the circular buffer memories and do you want 2048 or 4096 long memories.