RECALL the relation of address bit label to address bit value ------------------------------------------------------------- A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 9 8 7 6 5 4 3 2 1 0 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 2 1 5 2 1 6 3 1 8 4 2 1 5 2 1 6 3 1 8 4 2 1 5 2 1 6 3 1 8 4 2 1 G G 1 5 2 4 2 6 M M M M 1 5 2 4 2 6 1 0 0 0 1 5 2 4 2 6 2 6 8 M M M 2 6 8 K K K 9 9 4 2 2 6 8 M M M K K K 2 6 8 4 A configuration for a 4013L appears to be 30,966 decimal bytes long. This is less than 32k bytes which is 32,768 Tests of Dean's 133 about 3-DEC-1997 1. It just flashes its FAIL LED. Push the Abort button and then this FAIL LED flashes faster. 2. Add jumper J1 to make it Crate Controller. 3. Add J2 pins 1-2, and 3-4 to put the RAM at adrs $0 as seen by VME. 4. Still the same symptoms wrt FAIL LED 5. Move PROM's Was Now Is ------- ------- XU24 BUG open XU31 ROM BOOT BUG XU36 BUG open XU46 ROM Boot BUG Now it runs BUG-133 6. J18 is setup for mixed A24,A32 It is factory Default $0010 0000 to $00EF FFFF will be A24 which is what we need. J17 pull it off to force D16. Otherwise with bit A24 low it would be D32 in the range $0000 0000 to $00FF FFFF i.e. right where we need D16. 7. Now it is all Factory Default except: J17 as explaned above, J12 not all VME IRQ's have been enabled (but who cares), and J13 makes Port be look DTE not DCE but this is what we would like for down loading. NOTE: All of this configuration stuff is based on a 133-A20 book. We do not have a vinila 133 book. 8. VME Tests use a 214 as a target in its normal range $0030 0000 to $0030 7FFF. To setup the test: MTB 00300000 MTC 00307FFC MTD 0->16BIT, 1->32 BIT Tests: MTE, MTF, MTH, MTI, MTJ and then to loop LC MTE MTF .... 9. Try to discover the address map of the 133 Is it the same as the 1333-A20 ? $0000 0000 : $000F FFFF should be the 1 MByte of on card DRAM $0030 0000 : $0030 7FFF is working to VME $00EF FFF0 is a miss Starting at $00F0 0000 there is stuff but it is not Read/Write EPROM ? Main DRAM appears to repeat at $0100 0000, $0200 0000, $0300 0000 through $0E00 0000. Is it actually in each of these blocks 16 times ? All of this is very different than the CPU's view of address space in a 133-A20. Using a card base address of $0011 0000 puts this card's VME Interface FPGA in the range $0011 0000 through $0011 01FF. VME Interface Registers that we care about: Board Species ID $0011 0000 Board Condition Status Register $0011 0004 Chip 15:0 Configuration Enable Register $0011 0008 Chip 31:16 Configuration Enable Register $0011 000A Chip 15:0 Configured Register $0011 000C Chip 31:16 Configured Register $0011 000E Chip 15:0 Status Register $0011 0014 Chip 31:16 Status Register $0011 0016 Using a card base address of $0011 0000 puts this card's FPGA Configuration Addresses in the range $0011 7C00 through $0011 7DFF. Using a card base address of $0011 0000 puts this card's MSA #4 FPGA at a base address of $0011 1000. In the following, Number are in decimal unless marked with a $ for base 16. Register Number #8 VME Adrs $0011 1010 is Control Status Register for MSA #4. It is a 16 bit register. The bits are assigned in the following way: Read ONly MSA #4 Register Number #11 VME Adrs $0011 1016 is the control register in the Line Enable Control block. This register allows on to pick the number of ADC cycles before the Line Enable signal becomes active and then the number of ADC cycles before the Line Enable signal returns low. typical value 16,898 Using a card base address of $0011 0000 puts this card's BSF (Chip Number #17) at a base address of $0011 4400. In the following, Number are in decimal unless marked with a $ for base 16. BSF Register Number #8 VME Adrs $0011 4410 is the Global I/O Plus Control Status Register. It is a 16 bit register. The bits are assigned in the following way: typical value 8192 enable external integrate signal BSF Register Number #11 VME Adrs $0011 4416 is the control register in the Clock Generator Module. It picks the phase relationship between the Master Array Clock and the ADC Clock. This register picks the "begin pulse" and "end pulse" addresses for the Master Array Clock. typical value is 4353 BSF Register Number #14 VME Adrs $0011 441C is the Start ADC Clock Train Register. Typical value ~ 409 = $0199 BSF Register Number #17 VME Adrs $0011 4422 is the Stop ADC Clock Train Register. Typical value ~ 17,822 = $459E i.e. Readout in 17.6 msec. or is it 17,819