            Microtec Research Inc. ASM68020 V6.4  Page 1 Fri Jan 16 13:55:21 1998
 

Cmdline - dirac$dka100:[dept1_users.][edmunds.d068k.asm_vest]asm_68k_vested.exe;2 /flags=p=68020 steves_loader.src 
Line         Address
1                                       *************************************************************************
2                                       *                                                                       *
3                                       *                Steve's__68k_FPGA_Configuration_Service                *
4                                       *                                                                       *
5                                       *                  Version: 1         DATE:  23-DEC-1997                *
6                                       *                ----------------------------------------               *
7                                       *                                                                       *
8                                       *************************************************************************
9                                       
10                                      
11                                      
12                                      SER68_Main  IDNT                          ; title.
13                                                  ORG     $20000                ; start of code in the MVME133.
14                                      
15           00020000 4EF9 0002 0006                JMP     StrInt                ; Jump to the start of initialization.
16                                      
17                                      
18                                      *************************************************************************
19                                      *  This sections calls all of the include files and defines the Marcos. *
20                                      *                                                                       *
21                                      * e.g.    INCLUDE  my_68k.Include    ; Get the symbol file.             *
22                                      *************************************************************************
23                                      
24                                      
25                                      SoftWait   MACRO                      ; Software timer loop.
26                                                 LOCAL    WaitMore          ; Define a local symbol.
27                                                 MOVE.L   \1,D4             ; Load delay time  \1  into D4.
28                                      WaitMore   SUBI.L   #1,D4             ; Decrement loop counter.
29                                                 BNE      WaitMore          ; Test for end of delay.
30                                                 ENDM                       ; Called with an argument of
31                                                                            ; $1000 causes a delay of about
32                                                                            ; 3.0 mill second.  This routine
33                                                                            ; uses and destroys register D4.
34                                      
35                                      
36                                      *************************************************************************
37                                      *                                                                       *
38                                      *        **********     START OF THE PROGRAM     **********             *
39                                      *                                                                       *
40                                      *************************************************************************
41                                      *                                                                       *
42                                      *  Send the Wake-Up message to the L15CT console.                       *
43                                      *                                                                       *
44                                      *************************************************************************
45           00020006 4879 0002 01C8    StrInt  PEA.L   BlankLines              ; Clear the screen on
46           0002000C 4EB9 0000 0000  E         JSR     ChrStrgOut              ; the L15CT console.
47                                      
48           00020012 4879 0002 01DA            PEA.L   Hello                   ; Push the Hello message address on
49           00020018 4EB9 0000 0000  E         JSR     ChrStrgOut              ; the stack and send it out.
50                                      
51           0002001E 4879 0002 01D5            PEA.L   BlankLn                 ; Push the Blank Line address on the
52           00020024 4EB9 0000 0000  E         JSR     ChrStrgOut              ; stack and send it out.
53                                      
54                                      
            Microtec Research Inc. ASM68020 V6.4  Page 2 Fri Jan 16 13:55:21 1998
 

Line         Address
55                                      *************************************************************************
56                                      *  Configure the MSA #4 FPGA                                            *
57                                      *                                                                       *
58                                      *************************************************************************
59                                      
60                                      *****  Read the Board Condition Status Register and disable all  *****
61                                      *****  the MSA FPGA Outputs and the BSF FPGA outputs.            *****
62                                      
63           0002002A 4879 0002 020D            PEA.L    MsgDisOuts        ; Push the Disabling Outputs message
64           00020030 4EB9 0000 0000  E         JSR      ChrStrgOut        ; address on the stack and send it out.
65                                      
66           00020036 3039 0011 0004            Move.W   BrdCondStat,D0    ; Get the Board Condition Status Register
67           0002003C 0240 FFF3                 AndI.W   #$FFF3,D0         ; Mask off the MSA and BSF FPGA output
68                                                                         ;   enable bits, register bits (3:2)
69           00020040 33C0 0011 0004            Move.W   D0,BrdCondStat    ; Write the Board Condition Status Register
70                                                                         ;   back to the VME interface flga.
71                                      
72                                      *****  Enable Configuration of the  MSA4 FPGA chip #4       *****
73                                      
74           00020046 4879 0002 0240            PEA.L    MsgEnbCfg4        ; Push the Enabling Configuration Chip #4
75           0002004C 4EB9 0000 0000  E         JSR      ChrStrgOut        ; message adrs on the stack & send it out.
76                                      
77           00020052 33FC 0010 0011            Move.W   #$0010,Config150Enb    ; Select Chip #4 in the Chip 15:0
                      0008           
78                                                                              ;   Configuration Enable Register.
79                                      
80                                      *****  Program the Board Condition Status Register to globally   *****
81                                      *****  enable configuration by cycling the Global Configuration  *****
82                                      *****  Enable bit low, high, low  with appropriate delays.       *****
83                                      
84           0002005A 4879 0002 02A6            PEA.L    MsgGlbEnbCfg      ; Push the Globally Enabling Configuration
85           00020060 4EB9 0000 0000  E         JSR      ChrStrgOut        ; message adrs on the stack & send it out.
86                                      
87           00020066 3039 0011 0004            Move.W   BrdCondStat,D0    ; Get the Board Condition Status Register.
88                                      
89           0002006C 0240 FFFE                 AndI.W   #$FFFE,D0         ; Mask off the Global Config Enable Bit.
90           00020070 33C0 0011 0004            Move.W   D0,BrdCondStat    ; Write the Board Condition Status Register
91                                              SoftWait #$A000            ; Wait for 30 mill seconds.
91.1         00020076 283C 0000 A000               MOVE.L   #$A000,D4             ; Load delay time  \1  into D4.
91.2         0002007C 0484 0000 0001    ??0001   SUBI.L   #1,D4             ; Decrement loop counter.
91.3         00020082 66F8                         BNE      ??0001          ; Test for end of delay.
92                                      
93           00020084 0040 0001                 OrI.W    #$0001,D0         ; Force ON the Global Config Enable Bit.
94           00020088 33C0 0011 0004            Move.W   D0,BrdCondStat    ; Write the Board Condition Status Register
95                                              SoftWait #$A000            ; Wait for 30 mill seconds.
95.1         0002008E 283C 0000 A000               MOVE.L   #$A000,D4             ; Load delay time  \1  into D4.
95.2         00020094 0484 0000 0001    ??0002   SUBI.L   #1,D4             ; Decrement loop counter.
95.3         0002009A 66F8                         BNE      ??0002          ; Test for end of delay.
96                                      
97           0002009C 0240 FFFE                 AndI.W   #$FFFE,D0         ; Mask off the Global Config Enable Bit.
98           000200A0 33C0 0011 0004            Move.W   D0,BrdCondStat    ; Write the Board Condition Status Register
99                                              SoftWait #$A000            ; Wait for 30 mill seconds.
99.1         000200A6 283C 0000 A000               MOVE.L   #$A000,D4             ; Load delay time  \1  into D4.
99.2         000200AC 0484 0000 0001    ??0003   SUBI.L   #1,D4             ; Decrement loop counter.
99.3         000200B2 66F8                         BNE      ??0003          ; Test for end of delay.
            Microtec Research Inc. ASM68020 V6.4  Page 3 Fri Jan 16 13:55:21 1998
 

Line         Address
100                                     
101                                     *****  Now write the 30,966 bytes of Configuration data to the MSA4 FPGA.*****
102                                     *****  Recall that this must be written one byte at a time but that the  *****
103                                     *****  writes are Word writes.  Before each write you need to verify,    *****
104                                     *****  via the FPGA's Chip Status Register bit, that it is ready for     *****
105                                     *****  the next byte.                                                    *****
106                                     
107          000200B4 4879 0002 02D9            PEA.L    MsgCfging4               ; Push the Configuring Chip #4
108          000200BA 4EB9 0000 0000  E         JSR      ChrStrgOut               ; message adrs on the stack and
109                                                                               ; send it out.
110                                     
111          000200C0 4280                      Clr.L      D0                     ; D0 used to make Words from Bytes.
112          000200C2 207C 0008 0000            MoveA.L   #BA_MSA4_Code,A0        ; Get pointer to MSA4's Config Data.
113                                     
114                                             FOR.L  D2 = #0 TO #30995  DO.S    ; Loop over the 30996 decimal bytes
114.1        000200C8 7400                     MOVE.L #0,D2 ;>> FOR <<
114.2        000200CA 6002                     BRA.S ??0004 ;>> FOR <<
114.3        000200CC 5282              ??0005 ADD.L #1,D2 ;>> FOR <<
114.4        000200CE 0C82 0000 7913    ??0004 CMP.L #30995,D2 ;>> FOR <<
114.5        000200D4 6E2A                     BGT.S  ??0007 ;>> FOR <<
115                                                                               ; of Xilinx 4013 Configuration Data.
116          000200D6 1018                         Move.B   (A0)+,D0              ; Get a Config Data Byte into a
117          000200D8 33C0 0011 7C00               Move.W   D0,BrdConfigAdrs      ; Word and write the word to the
118                                                                               ; FPGA Configuration Data Adrs.
119                                     
120                                     ChkStat4   SoftWait  #$0004               ; Wait for Chip Status to have a
120.1        000200DE 7804                         MOVE.L   #$0004,D4             ; Load delay time  \1  into D4.
120.2        000200E0 0484 0000 0001    ??0008   SUBI.L   #1,D4             ; Decrement loop counter.
120.3        000200E6 66F8                         BNE      ??0008          ; Test for end of delay.
121                                                                               ;   chance to change, 3 usec wait.
122          000200E8 3239 0011 0014               Move.W   Chip150Status,D1      ; Get the Chip 15:0 Status Register
123          000200EE 0241 0010                    AndI.W   #$0010,D1             ; Mask all but Status from Chip #4.
124                                     
125                                                IF.W  D1 <NE> #$0010  THEN.S   ; Test MSA4 i.e. Chip #4 Status.
125.1        000200F2 0C41 0010                CMP.W #$0010,D1 ;>> IF <<
125.2        000200F6 6706                     BEQ.S  ??0009 ;>> IF <<
126          000200F8 4EF9 0002 00DE                 Jmp  ChkStat4                ; If it is NOT set then wait and
127                                                ENDI                           ; test it again.  If it is set then
127.1                                   ??0009 ;>> ENDI <<
128                                                                               ; move on to loading the next byte
129                                                                               ; of configuration data.
130                                             ENDF                              ; End of For Loop.
130.1        000200FE 60CC              ??0006 BRA ??0005 ;>> ENDF <<
130.2                                   ??0007 ;>> ENDF <<
131                                     
132                                     
133                                     *****  Disable Configuration of all FPGA's               *****
134                                     
135          00020100 4879 0002 033F            PEA.L    MsgDisabAllCfg           ; Push the Disabling Configuration
136          00020106 4EB9 0000 0000  E         JSR      ChrStrgOut               ;   off all FPGA's  message address
137                                                                               ;   on the stack and send it out.
138          0002010C 33FC 0000 0011            Move.W   #$0000,Config150Enb      ; Disable configuration of chips
                      0008           
139          00020114 33FC 0000 0011            Move.W   #$0000,Config3116Enb     ; 15:0 and 31:16.
                      000A           
            Microtec Research Inc. ASM68020 V6.4  Page 4 Fri Jan 16 13:55:21 1998
 

Line         Address
140                                     
141                                     
142                                     *************************************************************************
143                                     *                                                                       *
144                                     *  Display the "Configured Registers".                                  *
145                                     *  Enable the FPGA and Front Panel ECL Outputs.                         *
146                                     *  Show some messages  and  then exit to the Bug Monitor..              *
147                                     *                                                                       *
148                                     *************************************************************************
149                                     
150                                     *****  Display the Configured Registers for Chips 15:0.    *****
151                                     
152          0002011C 4879 0002 03A5            PEA.L   MsgCfgInfo150               ; Display the message about the
153          00020122 4EB9 0000 0000  E         JSR     ChrWrtOut                   ; Configured Status of Chips 15:0.
154                                     
155          00020128 3039 0011 000C            MOVE.W  Configured150,D0            ; Get the Configured 15:0 Reg.
156          0002012E 4840                      SWAP    D0                          ; Get it ready to print.
157                                     
158                                             FOR.L  D3 = #1 TO #4  DO.S          ; Loop for all 4 characters of
158.1        00020130 7601                     MOVE.L #1,D3 ;>> FOR <<
158.2        00020132 6002                     BRA.S ??0010 ;>> FOR <<
158.3        00020134 5283              ??0011 ADD.L #1,D3 ;>> FOR <<
158.4        00020136 0C83 0000 0004    ??0010 CMP.L #4,D3 ;>> FOR <<
158.5        0002013C 6E0C                     BGT.S  ??0013 ;>> FOR <<
159          0002013E E998                         ROL.L   #4,D0                    ; the FPGA Configured 15:0. Shift
160          00020140 2F00                         Move.L  D0,-(A7)                 ; left into position and push.
161          00020142 4EB9 0000 0000  E            JSR     BinASCII                 ; Convert to ASCII and send out.
162                                             ENDF
162.1        00020148 60EA              ??0012 BRA ??0011 ;>> ENDF <<
162.2                                   ??0013 ;>> ENDF <<
163                                     
164          0002014A 4879 0002 03C4            PEA.L    MsgInfo150P                ; Push the concluding part of the
165          00020150 4EB9 0000 0000  E         JSR      ChrStrgOut                 ; message about 15:0 Configured.
166                                     
167                                     
168                                     *****  Display the Configured Registers for Chips 31:16.    *****
169                                     
170          00020156 4879 0002 03DE            PEA.L   MsgCfgInfo3116              ; Display the message about the
171          0002015C 4EB9 0000 0000  E         JSR     ChrWrtOut                   ; Configured Status of Chips 31:16.
172                                     
173          00020162 3039 0011 000E            MOVE.W  Configured3116,D0           ; Get the Configured 31:16 Reg.
174          00020168 4840                      SWAP    D0                          ; Get it ready to print.
175                                     
176                                             FOR.L  D3 = #1 TO #4  DO.S          ; Loop for all 4 characters of
176.1        0002016A 7601                     MOVE.L #1,D3 ;>> FOR <<
176.2        0002016C 6002                     BRA.S ??0014 ;>> FOR <<
176.3        0002016E 5283              ??0015 ADD.L #1,D3 ;>> FOR <<
176.4        00020170 0C83 0000 0004    ??0014 CMP.L #4,D3 ;>> FOR <<
176.5        00020176 6E0C                     BGT.S  ??0017 ;>> FOR <<
177          00020178 E998                         ROL.L   #4,D0                    ; the FPGA Configured 31:16. Shift
178          0002017A 2F00                         Move.L  D0,-(A7)                 ; left into position and push.
179          0002017C 4EB9 0000 0000  E            JSR     BinASCII                 ; Convert to ASCII and send out.
180                                             ENDF
180.1        00020182 60EA              ??0016 BRA ??0015 ;>> ENDF <<
180.2                                   ??0017 ;>> ENDF <<
            Microtec Research Inc. ASM68020 V6.4  Page 5 Fri Jan 16 13:55:21 1998
 

Line         Address
181                                     
182          00020184 4879 0002 03FD            PEA.L    MsgInfo3116P               ; Push the concluding part of the
183          0002018A 4EB9 0000 0000  E         JSR      ChrStrgOut                 ; message about 31:16 Configured.
184                                     
185                                     
186                                     *****  Read the Board Condition Status Register          *****
187                                     *****  and enable the BSF FPGA outputs.                  *****
188                                     
189          00020190 4879 0002 0372            PEA.L    MsgEnbOuts        ; Push the Enabling Outputs message
190          00020196 4EB9 0000 0000  E         JSR      ChrStrgOut        ; address on the stack & send it out.
191                                     
192          0002019C 3039 0011 0004            Move.W   BrdCondStat,D0    ; Get the Board Condition Status Register
193          000201A2 0040 001C                 OrI.W    #$001C,D0         ; and OR the BSF and MSA FPGA output enable
194                                                                        ; and the Front ECL output enable bits into
195                                                                        ; the register bits: 4,3,2.
196          000201A6 33C0 0011 0004            Move.W   D0,BrdCondStat    ; Write the Board Condition Status Register
197                                                                        ;   back to the VME interface flga.
198                                     
199                                     *****  Stop and Send out a Message and then Return to the Bug Monitor   *****
200                                     
201          000201AC 4879 0002 01D5            PEA.L   BlankLn                 ; Push the Blank Line address on the
202          000201B2 4EB9 0000 0000  E         JSR     ChrStrgOut              ; stack and send it out.
203          000201B8 4879 0002 01D5            PEA.L   BlankLn                 ; Push the Blank Line address on the
204          000201BE 4EB9 0000 0000  E         JSR     ChrStrgOut              ; stack and send it out.
205                                     
206          000201C4 4E4F                      TRAP    #15                ; Trap to the Bug Monitor.
207          000201C6 0063                      DC.W    $0063              ; return to 133ABUG
208                                     
209                                     
210                                     
211                                     *************************************************************************
212                                     *  Define Constants:                                                    *
213                                     *                                                                       *
214                                     *  Data used to send messages to the L15CT console screen.              *
215                                     *                                                                       *
216                                     *************************************************************************
217                                     
218          000201C8 0C0A 0A0A 0A0A    BlankLines    DC.B    12,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A
                      0A0A 0A0A 0A0A 
                      0A             
219                                     
220          000201D5 0420 2020 20      BlankLn       DC.B     4,'    '
221                                     
222          000201DA 3253 7465 7665    Hello         DC.B    50,'Steves  68k_FPGA_Configuration_Service      Ver: 1'
                      7320 2036 386B 
                      5F46 5047 415F 
                      436F 6E66 6967 
                      7572 6174 696F 
                      6E5F 5365 7276 
                      6963 6520 2020 
                      2020 2056 6572 
                      3A20 31        
223                                     
224          0002020D 3244 6973 6162    MsgDisOuts    DC.B    50,'Disable all MSA4 and BSF FPGA Outputs.            '
                      6C65 2061 6C6C 
                      204D 5341 3420 
            Microtec Research Inc. ASM68020 V6.4  Page 6 Fri Jan 16 13:55:21 1998
 

Line         Address
                      616E 6420 4253 
                      4620 4650 4741 
                      204F 7574 7075 
                      7473 2E20 2020 
                      2020 2020 2020 
                      2020 20        
225                                     
226          00020240 3245 6E61 626C    MsgEnbCfg4    DC.B    50,'Enable Configuration of Chip #4, the MSA4 FPGA.   '
                      6520 436F 6E66 
                      6967 7572 6174 
                      696F 6E20 6F66 
                      2043 6869 7020 
                      2334 2C20 7468 
                      6520 4D53 4134 
                      2046 5047 412E 
                      2020 20        
227          00020273 3245 6E61 626C    MsgEnbCfg17   DC.B    50,'Enable Configuration of Chip #17, the BSF FPGA.   '
                      6520 436F 6E66 
                      6967 7572 6174 
                      696F 6E20 6F66 
                      2043 6869 7020 
                      2331 372C 2074 
                      6865 2042 5346 
                      2046 5047 412E 
                      2020 20        
228                                     
229          000202A6 3247 6C6F 6261    MsgGlbEnbCfg  DC.B    50,'Globally Enable Configuration of FPGAs.           '
                      6C6C 7920 456E 
                      6162 6C65 2043 
                      6F6E 6669 6775 
                      7261 7469 6F6E 
                      206F 6620 4650 
                      4741 732E 2020 
                      2020 2020 2020 
                      2020 20        
230                                     
231          000202D9 3243 6F6E 6669    MsgCfging4    DC.B    50,'Configure FPGA #4, the MSA4 FPGA.                 '
                      6775 7265 2046 
                      5047 4120 2334 
                      2C20 7468 6520 
                      4D53 4134 2046 
                      5047 412E 2020 
                      2020 2020 2020 
                      2020 2020 2020 
                      2020 20        
232          0002030C 3243 6F6E 6669    MsgCfging17   DC.B    50,'Configure FPGA #17, the BSF FPGA.                 '
                      6775 7265 2046 
                      5047 4120 2331 
                      372C 2074 6865 
                      2042 5346 2046 
                      5047 412E 2020 
                      2020 2020 2020 
                      2020 2020 2020 
                      2020 20        
233                                     
            Microtec Research Inc. ASM68020 V6.4  Page 7 Fri Jan 16 13:55:21 1998
 

Line         Address
234          0002033F 3244 6973 6162    MsgDisabAllCfg  DC.B  50,'Disable Configuration of All FPGAs.               '
                      6C65 2043 6F6E 
                      6669 6775 7261 
                      7469 6F6E 206F 
                      6620 416C 6C20 
                      4650 4741 732E 
                      2020 2020 2020 
                      2020 2020 2020 
                      2020 20        
235                                     
236          00020372 3245 6E61 626C    MsgEnbOuts    DC.B    50,'Enable BSF & MSA FPGA Outputs and Front ECL Output'
                      6520 4253 4620 
                      2620 4D53 4120 
                      4650 4741 204F 
                      7574 7075 7473 
                      2061 6E64 2046 
                      726F 6E74 2045 
                      434C 204F 7574 
                      7075 74        
237                                     
238          000203A5 1E20 2043 6F6E    MsgCfgInfo150   DC.B  30,'  Configured 15:0  Register = '
                      6669 6775 7265 
                      6420 3135 3A30 
                      2020 5265 6769 
                      7374 6572 203D 
                      20             
239          000203C4 1920 2020 2054    MsgInfo150P     DC.B  25,'    This should be $xx1x.'
                      6869 7320 7368 
                      6F75 6C64 2062 
                      6520 2478 7831 
                      782E           
240                                     
241          000203DE 1E20 2043 6F6E    MsgCfgInfo3116  DC.B  30,'  Configured 31:16 Register = '
                      6669 6775 7265 
                      6420 3331 3A31 
                      3620 5265 6769 
                      7374 6572 203D 
                      20             
242          000203FD 1920 2020 2054    MsgInfo3116P    DC.B  25,'    This should be $xxx2.'
                      6869 7320 7368 
                      6F75 6C64 2062 
                      6520 2478 7878 
                      322E           
243                                     
244                                     
245          00020418 0000 000F         Low4Long      DC.L    $0000000F        ; Low order 4 bits set Mask.
246                                                   XDEF    Low4Long
247                                     
248                                     
249          00110000                   FM_Base         EQU   $00110000         ; Base address of the FIRC FM THE-Card
250                                                                             ;   $00110000 is the adrs for slot 12
251                                                                             ;   this is up where the MVME-133 can
252                                                                             ;   get at it via VME.
253                                     
254                                     
            Microtec Research Inc. ASM68020 V6.4  Page 8 Fri Jan 16 13:55:21 1998
 

Line         Address
255          00110000                   BrdSpecID       EQU   FM_Base+$0000     ; VME IF Board Species ID Register
256          00110004                   BrdCondStat     EQU   FM_Base+$0004     ; Board Condition Status Register
257                                     
258          00110008                   Config150Enb    EQU   FM_Base+$0008     ; Chip 15:0 Configuration Enable Reg.
259          0011000A                   Config3116Enb   EQU   FM_Base+$000A     ; Chip 31:16 Configuration Enable Reg.
260                                     
261          0011000C                   Configured150   EQU   FM_Base+$000C     ; Chip 15:0 Configured Register
262          0011000E                   Configured3116  EQU   FM_Base+$000E     ; Chip 31:16 Configured Register
263                                     
264          00110014                   Chip150Status   EQU   FM_Base+$0014     ; Chip 15:0 Status Register
265          00110016                   Chip3116Status  EQU   FM_Base+$0016     ; Chip 31:16 Status Register
266                                     
267          00117C00                   BrdConfigAdrs   EQU   FM_Base+$7C00     ; Board FPGA Configuration Data Adrs
268                                     
269                                     
270          00111000                   MSA4_BA         EQU   FM_Base+$1000     ; Base addres of MSA4 FPGA
271                                     
272          00111010                   MSA4_Status     EQU   FM_Base+$1010     ; Control Status Register for MSA4
273                                                                             ;   Read Only   MSA4 Register #8
274                                     
275          00111016                   MSA4_LE_Ctrl    EQU   FM_Base+$1016     ; Control Register for the Line
276                                                                             ;   Enable Control Block. Selects
277                                                                             ;   the number of ADC Clk before LE
278                                                                             ;   is asserted and the number
279                                                                             ;   during LE's assertion.
280                                                                             ;   MSA4 Register #11
281                                     
282          0011101C                   MSA4_Frm_Start  EQU   FM_Base+$101C     ; MSA4 Register #14
283          00111022                   MSA4_Frm_Stop   EQU   FM_Base+$1022     ; MSA4 Register #17
284                                     
285                                     
286          00080000                   BA_MSA4_Code    EQU   $00080000         ; Base Address of MSA4's Configuration
287                                     
288                                     
289                                     
290                                     *************************************************************************
291                                     *  Define Constants:                                                    *
292                                     *                                                                       *
293                                     *  Specify the symbols to Import.                                       *
294                                     *************************************************************************
295                                     
296                                             XREF   ChrStrgOut                                   ; Symbols defined
297                                             XREF   ChrWrtOut                                    ; in other modules
298                                             XREF   BinASCII                                     ; and used in this
299                                                                                                 ; module.
300                                             END
            Microtec Research Inc. ASM68020 V6.4  Page 9 Fri Jan 16 13:55:21 1998
 

                   Symbol Table

Label               Value

BA_MSA4_CODE      00080000
BINASCII          External
BLANKLINES        000201C8
BLANKLN           000201D5
BRDCONDSTAT       00110004
BRDCONFIGADRS     00117C00
BRDSPECID         00110000
CHIP150STATUS     00110014
CHIP3116STATUS    00110016
CHKSTAT4          000200DE
CHRSTRGOUT        External
CHRWRTOUT         External
CONFIG150ENB      00110008
CONFIG3116ENB     0011000A
CONFIGURED150     0011000C
CONFIGURED3116    0011000E
FM_BASE           00110000
HELLO             000201DA
LOW4LONG          00020418
MSA4_BA           00111000
MSA4_FRM_START    0011101C
MSA4_FRM_STOP     00111022
MSA4_LE_CTRL      00111016
MSA4_STATUS       00111010
MSGCFGINFO150     000203A5
MSGCFGINFO3116    000203DE
MSGCFGING17       0002030C
MSGCFGING4        000202D9
MSGDISABALLCFG    0002033F
MSGDISOUTS        0002020D
MSGENBCFG17       00020273
MSGENBCFG4        00020240
MSGENBOUTS        00020372
MSGGLBENBCFG      000202A6
MSGINFO150P       000203C4
MSGINFO3116P      000203FD
SOFTWAIT            Macro 
STRINT            00020006


 Errors: 0, Warnings: 0
