*************************************************************************
*                                                                       *
*                Steve's__68k_FPGA_Configuration_Service                *
*                                                                       *
*                  Version: 1         DATE:  23-DEC-1997                *
*                ----------------------------------------               *
*                                                                       *
*************************************************************************



SER68_Main  IDNT                          ; title.
            ORG     $20000                ; start of code in the MVME133.

            JMP     StrInt                ; Jump to the start of initialization.


*************************************************************************
*  This sections calls all of the include files and defines the Marcos. *
*                                                                       *
* e.g.    INCLUDE  my_68k.Include    ; Get the symbol file.             *
*************************************************************************


SoftWait   MACRO                      ; Software timer loop.
           LOCAL    WaitMore          ; Define a local symbol.
           MOVE.L   \1,D4             ; Load delay time  \1  into D4.
WaitMore   SUBI.L   #1,D4             ; Decrement loop counter.
           BNE      WaitMore          ; Test for end of delay.
           ENDM                       ; Called with an argument of
                                      ; $1000 causes a delay of about
                                      ; 3.0 mill second.  This routine
                                      ; uses and destroys register D4.


*************************************************************************
*                                                                       *
*        **********     START OF THE PROGRAM     **********             *
*                                                                       *
*************************************************************************
*                                                                       *
*  Send the Wake-Up message to the L15CT console.                       *
*                                                                       *
*************************************************************************
StrInt  PEA.L   BlankLines              ; Clear the screen on
        JSR     ChrStrgOut              ; the L15CT console.

        PEA.L   Hello                   ; Push the Hello message address on
        JSR     ChrStrgOut              ; the stack and send it out.

        PEA.L   BlankLn                 ; Push the Blank Line address on the
        JSR     ChrStrgOut              ; stack and send it out.


*************************************************************************
*  Configure the MSA #4 FPGA                                            *
*                                                                       *
*************************************************************************

*****  Read the Board Condition Status Register and disable all  *****
*****  the MSA FPGA Outputs and the BSF FPGA outputs.            *****

        PEA.L    MsgDisOuts        ; Push the Disabling Outputs message
        JSR      ChrStrgOut        ; address on the stack and send it out.

        Move.W   BrdCondStat,D0    ; Get the Board Condition Status Register
        AndI.W   #$FFF3,D0         ; Mask off the MSA and BSF FPGA output
                                   ;   enable bits, register bits (3:2)
        Move.W   D0,BrdCondStat    ; Write the Board Condition Status Register
                                   ;   back to the VME interface flga.

*****  Enable Configuration of the  MSA4 FPGA chip #4       *****

        PEA.L    MsgEnbCfg4        ; Push the Enabling Configuration Chip #4
        JSR      ChrStrgOut        ; message adrs on the stack & send it out.

        Move.W   #$0010,Config150Enb    ; Select Chip #4 in the Chip 15:0
                                        ;   Configuration Enable Register.

*****  Program the Board Condition Status Register to globally   *****
*****  enable configuration by cycling the Global Configuration  *****
*****  Enable bit low, high, low  with appropriate delays.       *****

        PEA.L    MsgGlbEnbCfg      ; Push the Globally Enabling Configuration
        JSR      ChrStrgOut        ; message adrs on the stack & send it out.

        Move.W   BrdCondStat,D0    ; Get the Board Condition Status Register.

        AndI.W   #$FFFE,D0         ; Mask off the Global Config Enable Bit.
        Move.W   D0,BrdCondStat    ; Write the Board Condition Status Register
        SoftWait #$A000            ; Wait for 30 mill seconds.

        OrI.W    #$0001,D0         ; Force ON the Global Config Enable Bit.
        Move.W   D0,BrdCondStat    ; Write the Board Condition Status Register
        SoftWait #$A000            ; Wait for 30 mill seconds.

        AndI.W   #$FFFE,D0         ; Mask off the Global Config Enable Bit.
        Move.W   D0,BrdCondStat    ; Write the Board Condition Status Register
        SoftWait #$A000            ; Wait for 30 mill seconds.

*****  Now write the 30,966 bytes of Configuration data to the MSA4 FPGA.*****
*****  Recall that this must be written one byte at a time but that the  *****
*****  writes are Word writes.  Before each write you need to verify,    *****
*****  via the FPGA's Chip Status Register bit, that it is ready for     *****
*****  the next byte.                                                    *****

        PEA.L    MsgCfging4               ; Push the Configuring Chip #4
        JSR      ChrStrgOut               ; message adrs on the stack and
                                          ; send it out.

        Clr.L      D0                     ; D0 used to make Words from Bytes.
        MoveA.L   #BA_MSA4_Code,A0        ; Get pointer to MSA4's Config Data.

        FOR.L  D2 = #0 TO #30995  DO.S    ; Loop over the 30996 decimal bytes
                                          ; of Xilinx 4013 Configuration Data.
           Move.B   (A0)+,D0              ; Get a Config Data Byte into a
           Move.W   D0,BrdConfigAdrs      ; Word and write the word to the
                                          ; FPGA Configuration Data Adrs.

ChkStat4   SoftWait  #$0004               ; Wait for Chip Status to have a
                                          ;   chance to change, 3 usec wait.
           Move.W   Chip150Status,D1      ; Get the Chip 15:0 Status Register
           AndI.W   #$0010,D1             ; Mask all but Status from Chip #4.

           IF.W  D1 <NE> #$0010  THEN.S   ; Test MSA4 i.e. Chip #4 Status.
             Jmp  ChkStat4                ; If it is NOT set then wait and
           ENDI                           ; test it again.  If it is set then
                                          ; move on to loading the next byte
                                          ; of configuration data.
        ENDF                              ; End of For Loop.


*****  Disable Configuration of all FPGA's               *****

        PEA.L    MsgDisabAllCfg           ; Push the Disabling Configuration
        JSR      ChrStrgOut               ;   off all FPGA's  message address
                                          ;   on the stack and send it out.
        Move.W   #$0000,Config150Enb      ; Disable configuration of chips
        Move.W   #$0000,Config3116Enb     ; 15:0 and 31:16.


*************************************************************************
*                                                                       *
*  Display the "Configured Registers".                                  *
*  Enable the FPGA and Front Panel ECL Outputs.                         *
*  Show some messages  and  then exit to the Bug Monitor..              *
*                                                                       *
*************************************************************************

*****  Display the Configured Registers for Chips 15:0.    *****

        PEA.L   MsgCfgInfo150               ; Display the message about the
        JSR     ChrWrtOut                   ; Configured Status of Chips 15:0.

        MOVE.W  Configured150,D0            ; Get the Configured 15:0 Reg.
        SWAP    D0                          ; Get it ready to print.

        FOR.L  D3 = #1 TO #4  DO.S          ; Loop for all 4 characters of
           ROL.L   #4,D0                    ; the FPGA Configured 15:0. Shift
           Move.L  D0,-(A7)                 ; left into position and push.
           JSR     BinASCII                 ; Convert to ASCII and send out.
        ENDF

        PEA.L    MsgInfo150P                ; Push the concluding part of the
        JSR      ChrStrgOut                 ; message about 15:0 Configured.


*****  Display the Configured Registers for Chips 31:16.    *****

        PEA.L   MsgCfgInfo3116              ; Display the message about the
        JSR     ChrWrtOut                   ; Configured Status of Chips 31:16.

        MOVE.W  Configured3116,D0           ; Get the Configured 31:16 Reg.
        SWAP    D0                          ; Get it ready to print.

        FOR.L  D3 = #1 TO #4  DO.S          ; Loop for all 4 characters of
           ROL.L   #4,D0                    ; the FPGA Configured 31:16. Shift
           Move.L  D0,-(A7)                 ; left into position and push.
           JSR     BinASCII                 ; Convert to ASCII and send out.
        ENDF

        PEA.L    MsgInfo3116P               ; Push the concluding part of the
        JSR      ChrStrgOut                 ; message about 31:16 Configured.


*****  Read the Board Condition Status Register          *****
*****  and enable the BSF FPGA outputs.                  *****

        PEA.L    MsgEnbOuts        ; Push the Enabling Outputs message
        JSR      ChrStrgOut        ; address on the stack & send it out.

        Move.W   BrdCondStat,D0    ; Get the Board Condition Status Register
        OrI.W    #$001C,D0         ; and OR the BSF and MSA FPGA output enable
                                   ; and the Front ECL output enable bits into
                                   ; the register bits: 4,3,2.
        Move.W   D0,BrdCondStat    ; Write the Board Condition Status Register
                                   ;   back to the VME interface flga.

*****  Stop and Send out a Message and then Return to the Bug Monitor   *****

        PEA.L   BlankLn                 ; Push the Blank Line address on the
        JSR     ChrStrgOut              ; stack and send it out.
        PEA.L   BlankLn                 ; Push the Blank Line address on the
        JSR     ChrStrgOut              ; stack and send it out.

        TRAP    #15                ; Trap to the Bug Monitor.
        DC.W    $0063              ; return to 133ABUG



*************************************************************************
*  Define Constants:                                                    *
*                                                                       *
*  Data used to send messages to the L15CT console screen.              *
*                                                                       *
*************************************************************************

BlankLines    DC.B    12,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A

BlankLn       DC.B     4,'    '

Hello         DC.B    50,'Steves  68k_FPGA_Configuration_Service      Ver: 1'

MsgDisOuts    DC.B    50,'Disable all MSA4 and BSF FPGA Outputs.            '

MsgEnbCfg4    DC.B    50,'Enable Configuration of Chip #4, the MSA4 FPGA.   '
MsgEnbCfg17   DC.B    50,'Enable Configuration of Chip #17, the BSF FPGA.   '

MsgGlbEnbCfg  DC.B    50,'Globally Enable Configuration of FPGAs.           '

MsgCfging4    DC.B    50,'Configure FPGA #4, the MSA4 FPGA.                 '
MsgCfging17   DC.B    50,'Configure FPGA #17, the BSF FPGA.                 '

MsgDisabAllCfg  DC.B  50,'Disable Configuration of All FPGAs.               '

MsgEnbOuts    DC.B    50,'Enable BSF & MSA FPGA Outputs and Front ECL Output'

MsgCfgInfo150   DC.B  30,'  Configured 15:0  Register = '
MsgInfo150P     DC.B  25,'    This should be $xx1x.'

MsgCfgInfo3116  DC.B  30,'  Configured 31:16 Register = '
MsgInfo3116P    DC.B  25,'    This should be $xxx2.'


Low4Long      DC.L    $0000000F        ; Low order 4 bits set Mask.
              XDEF    Low4Long


FM_Base         EQU   $00110000         ; Base address of the FIRC FM THE-Card
                                        ;   $00110000 is the adrs for slot 12
                                        ;   this is up where the MVME-133 can
                                        ;   get at it via VME.


BrdSpecID       EQU   FM_Base+$0000     ; VME IF Board Species ID Register
BrdCondStat     EQU   FM_Base+$0004     ; Board Condition Status Register

Config150Enb    EQU   FM_Base+$0008     ; Chip 15:0 Configuration Enable Reg.
Config3116Enb   EQU   FM_Base+$000A     ; Chip 31:16 Configuration Enable Reg.

Configured150   EQU   FM_Base+$000C     ; Chip 15:0 Configured Register
Configured3116  EQU   FM_Base+$000E     ; Chip 31:16 Configured Register

Chip150Status   EQU   FM_Base+$0014     ; Chip 15:0 Status Register
Chip3116Status  EQU   FM_Base+$0016     ; Chip 31:16 Status Register

BrdConfigAdrs   EQU   FM_Base+$7C00     ; Board FPGA Configuration Data Adrs


MSA4_BA         EQU   FM_Base+$1000     ; Base addres of MSA4 FPGA

MSA4_Status     EQU   FM_Base+$1010     ; Control Status Register for MSA4
                                        ;   Read Only   MSA4 Register #8

MSA4_LE_Ctrl    EQU   FM_Base+$1016     ; Control Register for the Line
                                        ;   Enable Control Block. Selects
                                        ;   the number of ADC Clk before LE
                                        ;   is asserted and the number
                                        ;   during LE's assertion.
                                        ;   MSA4 Register #11

MSA4_Frm_Start  EQU   FM_Base+$101C     ; MSA4 Register #14
MSA4_Frm_Stop   EQU   FM_Base+$1022     ; MSA4 Register #17


BA_MSA4_Code    EQU   $00080000         ; Base Address of MSA4's Configuration



*************************************************************************
*  Define Constants:                                                    *
*                                                                       *
*  Specify the symbols to Import.                                       *
*************************************************************************

        XREF   ChrStrgOut                                   ; Symbols defined
        XREF   ChrWrtOut                                    ; in other modules
        XREF   BinASCII                                     ; and used in this
                                                            ; module.
        END

