************************************************************************* * * * 68k_FPGA_Configuration_Service * * * * Version: 1 DATE: 23-DEC-1997 * * ---------------------------------------- * * * ************************************************************************* SER68_Main IDNT ; title. ORG $10000 ; start of code in the MVME133. JMP StrInt ; Jump to the start of initialization. ************************************************************************* * This sections calls all of the include files and defines the Marcos. * * * * e.g. INCLUDE my_68k.Include ; Get the symbol file. * ************************************************************************* SoftWait MACRO ; Software timer loop. LOCAL WaitMore ; Define a local symbol. MOVE.L \1,D4 ; Load delay time \1 into D4. WaitMore SUBI.L #1,D4 ; Decrement loop counter. BNE WaitMore ; Test for end of delay. ENDM ; Called with an argument of ; $1000 causes a delay of about ; 3.0 mill second. This routine ; uses and destroys register D4. ************************************************************************* * * * ********** START OF THE PROGRAM ********** * * * ************************************************************************* * * * Send the Wake-Up message to the L15CT console. * * * ************************************************************************* StrInt PEA.L BlankLines ; Clear the screen on JSR ChrStrgOut ; the L15CT console. PEA.L Hello ; Push the Hello message address on JSR ChrStrgOut ; the stack and send it out. PEA.L BlankLn ; Push the Blank Line address on the JSR ChrStrgOut ; stack and send it out. ************************************************************************* * Configure the BSF FPGA * * * ************************************************************************* ***** Read the Board Condition Status Register and disable all ***** ***** the MSA FPGA Outputs and the BSF FPGA outputs. ***** PEA.L MsgDisOuts ; Push the Disabling Outputs message JSR ChrStrgOut ; address on the stack and send it out. Move.W BrdCondStat,D0 ; Get the Board Condition Status Register AndI.W #$FFF3,D0 ; Mask off the MSA and BSF FPGA output ; enable bits, register bits (3:2) Move.W D0,BrdCondStat ; Write the Board Condition Status Register ; back to the VME interface flga. ***** Enable Configuration of the BSF FPGA chip #17 ***** PEA.L MsgEnbCfg17 ; Push the Enabling Configuration Chip #17 JSR ChrStrgOut ; message adrs on the stack & send it out. Move.W #$0002,Config3116Enb ; Select Chip #17 in the Chip 31:16 ; Configuration Enable Register. ***** Program the Board Condition Status Register to globally ***** ***** enable configuration by cycling the Global Configuration ***** ***** Enable bit low, high, low with appropriate delays. ***** PEA.L MsgGlbEnbCfg ; Push the Globally Enabling Configuration JSR ChrStrgOut ; message adrs on the stack & send it out. Move.W BrdCondStat,D0 ; Get the Board Condition Status Register. AndI.W #$FFFE,D0 ; Mask off the Global Config Enable Bit. Move.W D0,BrdCondStat ; Write the Board Condition Status Register SoftWait #$A000 ; Wait for 30 mill seconds. OrI.W #$0001,D0 ; Force ON the Global Config Enable Bit. Move.W D0,BrdCondStat ; Write the Board Condition Status Register SoftWait #$A000 ; Wait for 30 mill seconds. AndI.W #$FFFE,D0 ; Mask off the Global Config Enable Bit. Move.W D0,BrdCondStat ; Write the Board Condition Status Register SoftWait #$A000 ; Wait for 30 mill seconds. ***** Now write the 30,966 bytes of Configuration data to the BSF FPGA. ***** ***** Recall that this must be written one byte at a time but that the ***** ***** writes are Word writes. Before each write you need to verify, ***** ***** via the FPGA's Chip Status Register bit, that it is ready for ***** ***** the next byte. ***** PEA.L MsgCfging17 ; Push the Configuring Chip #17 JSR ChrStrgOut ; message adrs on the stack and ; send it out. Clr.L D0 ; D0 used to make Words from Bytes. MoveA.L #BA_BSF_Code,A0 ; Get pointer to BSF's Config Data. FOR.L D2 = #0 TO #30995 DO.S ; Loop over the 30996 decimal bytes ; of Xilinx 4013 Configuration Data. Move.B (A0)+,D0 ; Get a Config Data Byte into a Move.W D0,BrdConfigAdrs ; Word and write the word to the ; FPGA Configuration Data Adrs. ChkStat17 SoftWait #$0004 ; Wait for Chip Status to have a ; chance to change, 3 usec wait. Move.W Chip3116Status,D1 ; Get the Chip 31:16 Status Register AndI.W #$0002,D1 ; Mask all but Status from Chip #17. IF.W D1 #$0002 THEN.S ; Test BSF i.e. Chip #17 Status. Jmp ChkStat17 ; If it is NOT set then wait and ENDI ; test it again. If it is set then ; move on to loading the next byte ; of configuration data. ENDF ; End of For Loop. ***** Disable Configuration of all FPGA's ***** PEA.L MsgDisabAllCfg ; Push the Disabling Configuration JSR ChrStrgOut ; off all FPGA's message address ; on the stack and send it out. Move.W #$0000,Config150Enb ; Disable configuration of chips Move.W #$0000,Config3116Enb ; 15:0 and 31:16. ************************************************************************* * Configure the MSA #4 FPGA * * * ************************************************************************* ***** Read the Board Condition Status Register and disable all ***** ***** the MSA FPGA Outputs and the BSF FPGA outputs. ***** PEA.L MsgDisOuts ; Push the Disabling Outputs message JSR ChrStrgOut ; address on the stack and send it out. Move.W BrdCondStat,D0 ; Get the Board Condition Status Register AndI.W #$FFF3,D0 ; Mask off the MSA and BSF FPGA output ; enable bits, register bits (3:2) Move.W D0,BrdCondStat ; Write the Board Condition Status Register ; back to the VME interface flga. ***** Enable Configuration of the MSA4 FPGA chip #4 ***** PEA.L MsgEnbCfg4 ; Push the Enabling Configuration Chip #4 JSR ChrStrgOut ; message adrs on the stack & send it out. Move.W #$0010,Config150Enb ; Select Chip #4 in the Chip 15:0 ; Configuration Enable Register. ***** Program the Board Condition Status Register to globally ***** ***** enable configuration by cycling the Global Configuration ***** ***** Enable bit low, high, low with appropriate delays. ***** PEA.L MsgGlbEnbCfg ; Push the Globally Enabling Configuration JSR ChrStrgOut ; message adrs on the stack & send it out. Move.W BrdCondStat,D0 ; Get the Board Condition Status Register. AndI.W #$FFFE,D0 ; Mask off the Global Config Enable Bit. Move.W D0,BrdCondStat ; Write the Board Condition Status Register SoftWait #$A000 ; Wait for 30 mill seconds. OrI.W #$0001,D0 ; Force ON the Global Config Enable Bit. Move.W D0,BrdCondStat ; Write the Board Condition Status Register SoftWait #$A000 ; Wait for 30 mill seconds. AndI.W #$FFFE,D0 ; Mask off the Global Config Enable Bit. Move.W D0,BrdCondStat ; Write the Board Condition Status Register SoftWait #$A000 ; Wait for 30 mill seconds. ***** Now write the 30,966 bytes of Configuration data to the MSA4 FPGA.***** ***** Recall that this must be written one byte at a time but that the ***** ***** writes are Word writes. Before each write you need to verify, ***** ***** via the FPGA's Chip Status Register bit, that it is ready for ***** ***** the next byte. ***** PEA.L MsgCfging4 ; Push the Configuring Chip #4 JSR ChrStrgOut ; message adrs on the stack and ; send it out. Clr.L D0 ; D0 used to make Words from Bytes. MoveA.L #BA_MSA4_Code,A0 ; Get pointer to MSA4's Config Data. FOR.L D2 = #0 TO #30995 DO.S ; Loop over the 30996 decimal bytes ; of Xilinx 4013 Configuration Data. Move.B (A0)+,D0 ; Get a Config Data Byte into a Move.W D0,BrdConfigAdrs ; Word and write the word to the ; FPGA Configuration Data Adrs. ChkStat4 SoftWait #$0004 ; Wait for Chip Status to have a ; chance to change, 3 usec wait. Move.W Chip150Status,D1 ; Get the Chip 15:0 Status Register AndI.W #$0010,D1 ; Mask all but Status from Chip #4. IF.W D1 #$0010 THEN.S ; Test MSA4 i.e. Chip #4 Status. Jmp ChkStat4 ; If it is NOT set then wait and ENDI ; test it again. If it is set then ; move on to loading the next byte ; of configuration data. ENDF ; End of For Loop. ***** Disable Configuration of all FPGA's ***** PEA.L MsgDisabAllCfg ; Push the Disabling Configuration JSR ChrStrgOut ; off all FPGA's message address ; on the stack and send it out. Move.W #$0000,Config150Enb ; Disable configuration of chips Move.W #$0000,Config3116Enb ; 15:0 and 31:16. ************************************************************************* * * * Display the "Configured Registers". * * Enable the FPGA and Front Panel ECL Outputs. * * Show some messages and then exit to the Bug Monitor.. * * * ************************************************************************* ***** Display the Configured Registers for Chips 15:0. ***** PEA.L MsgCfgInfo150 ; Display the message about the JSR ChrWrtOut ; Configured Status of Chips 15:0. MOVE.W Configured150,D0 ; Get the Configured 15:0 Reg. SWAP D0 ; Get it ready to print. FOR.L D3 = #1 TO #4 DO.S ; Loop for all 4 characters of ROL.L #4,D0 ; the FPGA Configured 15:0. Shift Move.L D0,-(A7) ; left into position and push. JSR BinASCII ; Convert to ASCII and send out. ENDF PEA.L MsgInfo150P ; Push the concluding part of the JSR ChrStrgOut ; message about 15:0 Configured. ***** Display the Configured Registers for Chips 31:16. ***** PEA.L MsgCfgInfo3116 ; Display the message about the JSR ChrWrtOut ; Configured Status of Chips 31:16. MOVE.W Configured3116,D0 ; Get the Configured 31:16 Reg. SWAP D0 ; Get it ready to print. FOR.L D3 = #1 TO #4 DO.S ; Loop for all 4 characters of ROL.L #4,D0 ; the FPGA Configured 31:16. Shift Move.L D0,-(A7) ; left into position and push. JSR BinASCII ; Convert to ASCII and send out. ENDF PEA.L MsgInfo3116P ; Push the concluding part of the JSR ChrStrgOut ; message about 31:16 Configured. ***** Read the Board Condition Status Register ***** ***** and enable the BSF FPGA outputs. ***** PEA.L MsgEnbOuts ; Push the Enabling Outputs message JSR ChrStrgOut ; address on the stack & send it out. Move.W BrdCondStat,D0 ; Get the Board Condition Status Register OrI.W #$001C,D0 ; and OR the BSF and MSA FPGA output enable ; and the Front ECL output enable bits into ; the register bits: 4,3,2. Move.W D0,BrdCondStat ; Write the Board Condition Status Register ; back to the VME interface flga. ***** Stop and Send out a Message and then Return to the Bug Monitor ***** PEA.L BlankLn ; Push the Blank Line address on the JSR ChrStrgOut ; stack and send it out. PEA.L MsgRoutines1 ; Push the Routines 1 message JSR ChrStrgOut ; address on the stack & send it out. PEA.L MsgRoutines2 ; Push the Routines 2 message JSR ChrStrgOut ; address on the stack & send it out. PEA.L MsgRoutines3 ; Push the Routines 3 message JSR ChrStrgOut ; address on the stack & send it out. PEA.L BlankLn ; Push the Blank Line address on the JSR ChrStrgOut ; stack and send it out. PEA.L BlankLn ; Push the Blank Line address on the JSR ChrStrgOut ; stack and send it out. TRAP #15 ; Trap to the Bug Monitor. DC.W $0063 ; return to 133ABUG ************************************************************************* * Load Registers Section * * * * Load the BSF and MSA4 Registers * * * ************************************************************************* ORG $12000 ; start the register load section PEA.L BlankLn ; Push the Blank Line address on the JSR ChrStrgOut ; stack and send it out. PEA.L BlankLn ; Push the Blank Line address on the JSR ChrStrgOut ; stack and send it out. PEA.L MsgLdReg0 ; Push the Load Registers 0 message JSR ChrStrgOut ; address on the stack & send it out. PEA.L BlankLn ; Push the Blank Line address on the JSR ChrStrgOut ; stack and send it out. PEA.L MsgLdReg1 ; Push the Load Registers 1 message JSR ChrStrgOut ; address on the stack & send it out. Move.W #$4202,MSA4_LE_Ctrl ; Load the Line Enable Control Register ; for 2 ADC pulses before LE active and ; LE returns inactive at 66 ADC pulses. PEA.L MsgLdReg2 ; Push the Load Registers 2 message JSR ChrStrgOut ; address on the stack & send it out. Move.W #$0001,MSA4_Frm_Start ; Load the Frame Enable Start Register ; to assert Frame Enable after 1 Quad ; Done pulse. PEA.L MsgLdReg3 ; Push the Load Registers 3 message JSR ChrStrgOut ; address on the stack & send it out. Move.W #$43FF,MSA4_Frm_Stop ; Load the Frame Enable Stop Register ; to negate Frame Enable after 17,407 ; Quad Done pulses. PEA.L MsgLdReg4 ; Push the Load Registers 4 message JSR ChrStrgOut ; address on the stack & send it out. Move.W #$1101,BSF_MClk_Phase ; Load the BSF Clock Generator Control ; Register. ADC Clk is 937 nsec after ; Master Array Clock. PEA.L MsgLdReg5 ; Push the Load Registers 5 message JSR ChrStrgOut ; address on the stack & send it out. Move.W #$019A,BSF_Start_ADC ; Load the BSF Start ADC Clk Register. ; Start ADC Clock after 410 ticks. PEA.L MsgLdReg6 ; Push the Load Registers 6 message JSR ChrStrgOut ; address on the stack & send it out. Move.W #$459C,BSF_Stop_ADC ; Load the BSF Stops ADC Clk Register. ; Stop ADC Clock after 17,820 ticks. PEA.L MsgLdReg7a ; Push the Load Registers 7a message JSR ChrStrgOut ; address on the stack & send it out. PEA.L MsgLdReg7b ; Push the Load Registers 7b message JSR ChrStrgOut ; address on the stack & send it out. Move.W #$2000,BSF_GlbIO_CSR ; Load the BSF Ctrl/Stat/Glb-IO Reg. ; Enable the External Integrate ; Signal PEA.L BlankLn ; Push the Blank Line address on the JSR ChrStrgOut ; stack and send it out. PEA.L BlankLn ; Push the Blank Line address on the JSR ChrStrgOut ; stack and send it out. TRAP #15 ; Trap to the Bug Monitor. DC.W $0063 ; return to 133ABUG ************************************************************************* * Display the Registers Section * * * * Display the content of the MSA4 and BSF Registers. * * * ************************************************************************* ORG $14000 ; start the register Display section PEA.L BlankLn ; Push the Blank Line address on the JSR ChrStrgOut ; stack and send it out. PEA.L BlankLn ; Push the Blank Line address on the JSR ChrStrgOut ; stack and send it out. PEA.L MsgRegDspl1 ; Push the Display Registers 1 message JSR ChrStrgOut ; address on the stack & send it out. PEA.L BlankLn ; Push the Blank Line address on the JSR ChrStrgOut ; stack and send it out. ***** Display the MSA4 Status Register MSA4 Reg #8 ***** PEA.L MsgRegDspl2a ; Display the message that begins JSR ChrWrtOut ; the MSA4 Status Reg Display. MOVE.W MSA4_Status,D0 ; Get the MSA4 Status Register. SWAP D0 ; Get it ready to print. FOR.L D3 = #1 TO #4 DO.S ; Loop for all 4 characters of ROL.L #4,D0 ; the this 16 bit register. Shift Move.L D0,-(A7) ; left into position and push. JSR BinASCII ; Convert to ASCII and send out. ENDF PEA.L MsgRegDspl2b ; Push the concluding part of the JSR ChrStrgOut ; message about MSA4 Status Reg. ***** Display the MSA4 Line Enable Control Register MSA4 Reg #11 ***** PEA.L MsgRegDspl3a ; Display the message that begins JSR ChrWrtOut ; the MSA4 Line Enable Control Reg MOVE.W MSA4_LE_Ctrl,D0 ; Get the MSA4 Line Enable Control SWAP D0 ; Get it ready to print. FOR.L D3 = #1 TO #4 DO.S ; Loop for all 4 characters of ROL.L #4,D0 ; the this 16 bit register. Shift Move.L D0,-(A7) ; left into position and push. JSR BinASCII ; Convert to ASCII and send out. ENDF PEA.L MsgRegDspl3b ; Push the concluding part of the JSR ChrStrgOut ; message about MSA4 LE Ctrl Reg. ***** Display the MSA4 Frame Enable Start Register MSA4 Reg #14 ***** PEA.L MsgRegDspl4a ; Display the message that begins JSR ChrWrtOut ; the MSA4 Frame Enb Start Reg. MOVE.W MSA4_Frm_Start,D0 ; Get the MSA4 Frame Start Reg. SWAP D0 ; Get it ready to print. FOR.L D3 = #1 TO #4 DO.S ; Loop for all 4 characters of ROL.L #4,D0 ; the this 16 bit register. Shift Move.L D0,-(A7) ; left into position and push. JSR BinASCII ; Convert to ASCII and send out. ENDF PEA.L MsgRegDspl4b ; Push the concluding part of the JSR ChrStrgOut ; message about MSA4 Frm Enb Reg. ***** Display the MSA4 Frame Enable Stop Register MSA4 Reg #17 ***** PEA.L MsgRegDspl5a ; Display the message that begins JSR ChrWrtOut ; the MSA4 Frame Enb Stop Reg. MOVE.W MSA4_Frm_Stop,D0 ; Get the MSA4 Frame Enb Stop Reg. SWAP D0 ; Get it ready to print. FOR.L D3 = #1 TO #4 DO.S ; Loop for all 4 characters of ROL.L #4,D0 ; the this 16 bit register. Shift Move.L D0,-(A7) ; left into position and push. JSR BinASCII ; Convert to ASCII and send out. ENDF PEA.L MsgRegDspl5b ; Push the concluding part of the JSR ChrStrgOut ; message about MSA4 Frm Enb Stop. ***** Display the BSF Global I/O Crtl/Status Register BSF Reg #8 ***** PEA.L MsgRegDspl6a ; Display the message that begins JSR ChrWrtOut ; the BSF Glb I/O Ctrl/Status Reg. MOVE.W BSF_GlbIO_CSR,D0 ; Get the Glb I/O Ctrl/Stat Reg. SWAP D0 ; Get it ready to print. FOR.L D3 = #1 TO #4 DO.S ; Loop for all 4 characters of ROL.L #4,D0 ; the this 16 bit register. Shift Move.L D0,-(A7) ; left into position and push. JSR BinASCII ; Convert to ASCII and send out. ENDF PEA.L MsgRegDspl6b ; Push the concluding part of the JSR ChrStrgOut ; message about BSF Glb IO CSR. ***** Display the BSF Master Array Clock Phase Register BSF Reg #11 ***** PEA.L MsgRegDspl7a ; Display the message that begins JSR ChrWrtOut ; the BSF Master Clock Phase Reg. MOVE.W BSF_MClk_Phase,D0 ; Get the BSF MClkc Phase Reg. SWAP D0 ; Get it ready to print. FOR.L D3 = #1 TO #4 DO.S ; Loop for all 4 characters of ROL.L #4,D0 ; the this 16 bit register. Shift Move.L D0,-(A7) ; left into position and push. JSR BinASCII ; Convert to ASCII and send out. ENDF PEA.L MsgRegDspl7b ; Push the concluding part of the JSR ChrStrgOut ; message about BSF MClk Phase. ***** Display the BSF Start ADC Clock Register BSF Reg #14 ***** PEA.L MsgRegDspl8a ; Display the message that begins JSR ChrWrtOut ; the BSF Start ADC Clock Reg. MOVE.W BSF_Start_ADC,D0 ; Get the BSF Start ADC Clock Reg. SWAP D0 ; Get it ready to print. FOR.L D3 = #1 TO #4 DO.S ; Loop for all 4 characters of ROL.L #4,D0 ; the this 16 bit register. Shift Move.L D0,-(A7) ; left into position and push. JSR BinASCII ; Convert to ASCII and send out. ENDF PEA.L MsgRegDspl8b ; Push the concluding part of the JSR ChrStrgOut ; message about BSF Start ADC Reg. ***** Display the BSF Stop ADC Clock Register BSF Reg #17 ***** PEA.L MsgRegDspl9a ; Display the message that begins JSR ChrWrtOut ; the BSF Stop ADC Clock Reg. MOVE.W BSF_Stop_ADC,D0 ; Get the BSF Stop ADC Clock Reg. SWAP D0 ; Get it ready to print. FOR.L D3 = #1 TO #4 DO.S ; Loop for all 4 characters of ROL.L #4,D0 ; the this 16 bit register. Shift Move.L D0,-(A7) ; left into position and push. JSR BinASCII ; Convert to ASCII and send out. ENDF PEA.L MsgRegDspl9b ; Push the concluding part of the JSR ChrStrgOut ; message about BSF Stop ADC Reg. ***** That all the registers so now exit to the Bug Monitor ***** PEA.L BlankLn ; Push the Blank Line address on the JSR ChrStrgOut ; stack and send it out. PEA.L BlankLn ; Push the Blank Line address on the JSR ChrStrgOut ; stack and send it out. TRAP #15 ; Trap to the Bug Monitor. DC.W $0063 ; return to 133ABUG ************************************************************************* * Cycle the Integrate Signal * * * * Disable the External Integrate Signal and generate an Internal * * Integrate of 0.1 sec duration at 1 Hz rate. * * Push the MVME-133 Abort Button when you are done with this test. * ************************************************************************* ORG $16000 ; start the register load section PEA.L BlankLn ; Push the Blank Line address on the JSR ChrStrgOut ; stack and send it out. PEA.L BlankLn ; Push the Blank Line address on the JSR ChrStrgOut ; stack and send it out. PEA.L MsgCycIntg1 ; Push the Cycle Integrate message #1 JSR ChrStrgOut ; address on the stack & send it out. PEA.L MsgCycIntg2 ; Push the Cycle Integrate message #2 JSR ChrStrgOut ; address on the stack & send it out. PEA.L MsgCycIntg3 ; Push the Cycle Integrate message #3 JSR ChrStrgOut ; address on the stack & send it out. PEA.L BlankLn ; Push the Blank Line address on the JSR ChrStrgOut ; stack and send it out. Move.W #$0000,BSF_GlbIO_CSR ; Load the BSF Ctrl/Stat/Glb-IO Reg. ; with zero, disable all Integrate. I_Cyc SoftWait #$FF00 ; Wait for 100 mill seconds. SoftWait #$FF00 ; Wait for 100 mill seconds. SoftWait #$FF00 ; Wait for 100 mill seconds. SoftWait #$FF00 ; Wait for 100 mill seconds. SoftWait #$FF00 ; Wait for 100 mill seconds. SoftWait #$FF00 ; Wait for 100 mill seconds. SoftWait #$FF00 ; Wait for 100 mill seconds. SoftWait #$FF00 ; Wait for 100 mill seconds. SoftWait #$FF00 ; Wait for 100 mill seconds. Move.W #$1000,BSF_GlbIO_CSR ; Load the BSF Ctrl/Stat/Glb-IO Reg. ; with $1000 to enable the Internal ; Integrate signal. SoftWait #$FF00 ; Wait for 100 mill seconds. Move.W #$0000,BSF_GlbIO_CSR ; Load the BSF Ctrl/Stat/Glb-IO Reg. ; with zero, disable all Integrate. JMP I_Cyc ; Cycle the Internal Integrate again. ************************************************************************* * Define Constants: * * * * Data used to send messages to the L15CT console screen. * * * ************************************************************************* BlankLines DC.B 12,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A BlankLn DC.B 4,' ' Hello DC.B 50,'68k_FPGA_Configuration_Service Fast IR Ver: 1' MsgDisOuts DC.B 50,'Disable all MSA4 and BSF FPGA Outputs. ' MsgEnbCfg4 DC.B 50,'Enable Configuration of Chip #4, the MSA4 FPGA. ' MsgEnbCfg17 DC.B 50,'Enable Configuration of Chip #17, the BSF FPGA. ' MsgGlbEnbCfg DC.B 50,'Globally Enable Configuration of FPGAs. ' MsgCfging4 DC.B 50,'Configure FPGA #4, the MSA4 FPGA. ' MsgCfging17 DC.B 50,'Configure FPGA #17, the BSF FPGA. ' MsgDisabAllCfg DC.B 50,'Disable Configuration of All FPGAs. ' MsgEnbOuts DC.B 50,'Enable BSF & MSA FPGA Outputs and Front ECL Output' MsgCfgInfo150 DC.B 30,' Configured 15:0 Register = ' MsgInfo150P DC.B 25,' This should be $xx1x.' MsgCfgInfo3116 DC.B 30,' Configured 31:16 Register = ' MsgInfo3116P DC.B 25,' This should be $xxx2.' MsgRoutines1 DC.B 50,'Go at 12000 to Load the BSF and MSA4 Registers. ' MsgRoutines2 DC.B 50,'Go at 14000 to Display the BSF and MSA4 Registers.' MsgRoutines3 DC.B 50,'Go at 16000 to Cycle the Internal Integrate Signal' MsgLdReg0 DC.B 50,'Load the MSA4 & BSF FPGA Registers on the FIRC FM.' MsgLdReg1 DC.B 50,'Load MSA4 Line Enable Ctrl $4202, on @ 2 off @ 66.' MsgLdReg2 DC.B 50,'Load MSA4 Frame Enb Start $0001, Start after 1 QD' MsgLdReg3 DC.B 50,'Load MSA4 Frame Enb Stop $43FF, Stop aftr 17407 QD' MsgLdReg4 DC.B 50,'Load BSF Clock Phase with $1101, delay ADC 937 ns.' MsgLdReg5 DC.B 50,'Load BSF Start ADC with $019A, Start ADC at 410. ' MsgLdReg6 DC.B 50,'Load BSF Stop ADC with $459C, Stop ADC at 17,820. ' MsgLdReg7a DC.B 50,'Load BSF CtrlStat Global I/O $2000, Enb Ext Intgr.' MsgLdReg7b DC.B 50,'This sets the TCM-2620: 100 fFd Cap & 100 usec SH.' MsgRegDspl1 DC.B 50,'This is the MSA4 and BSF Register Display Routine.' MsgRegDspl2a DC.B 30,' MSA4 Status Register = $' MsgRegDspl2b DC.B 25,' This is MSA4 Reg #8. ' MsgRegDspl3a DC.B 30,' MSA4 Line Enable Control = $' MsgRegDspl3b DC.B 25,' This is MSA4 Reg #11.' MsgRegDspl4a DC.B 30,' MSA4 Frame Enable Start = $' MsgRegDspl4b DC.B 25,' This is MSA4 Reg #14.' MsgRegDspl5a DC.B 30,' MSA4 Frame Enable Stop = $' MsgRegDspl5b DC.B 25,' This is MSA4 Reg #17.' MsgRegDspl6a DC.B 30,' BSF Global-I/O CSR Reg = $' MsgRegDspl6b DC.B 25,' This is BSF Reg #8. ' MsgRegDspl7a DC.B 30,' BSF Master Clk Phase Reg = $' MsgRegDspl7b DC.B 25,' This is BSF Reg #11. ' MsgRegDspl8a DC.B 30,' BSF Start ADC Clock Reg = $' MsgRegDspl8b DC.B 25,' This is BSF Reg #14. ' MsgRegDspl9a DC.B 30,' BSF Stop ADC Clock Reg = $' MsgRegDspl9b DC.B 25,' This is BSF Reg #17. ' MsgCycIntg1 DC.B 50,'Cycle the Internal Integrate Signal. Integrate ' MsgCycIntg2 DC.B 50,'for 0.1 second at a 1 Hz rate. Push the black ' MsgCycIntg3 DC.B 50,'Abort button on the MVME-133 when finished. ' Low4Long DC.L $0000000F ; Low order 4 bits set Mask. XDEF Low4Long FM_Base EQU $00110000 ; Base address of the FIRC FM THE-Card ; $00110000 is the adrs for slot 12 ; this is up where the MVME-133 can ; get at it via VME. BrdSpecID EQU FM_Base+$0000 ; VME IF Board Species ID Register BrdCondStat EQU FM_Base+$0004 ; Board Condition Status Register Config150Enb EQU FM_Base+$0008 ; Chip 15:0 Configuration Enable Reg. Config3116Enb EQU FM_Base+$000A ; Chip 31:16 Configuration Enable Reg. Configured150 EQU FM_Base+$000C ; Chip 15:0 Configured Register Configured3116 EQU FM_Base+$000E ; Chip 31:16 Configured Register Chip150Status EQU FM_Base+$0014 ; Chip 15:0 Status Register Chip3116Status EQU FM_Base+$0016 ; Chip 31:16 Status Register BrdConfigAdrs EQU FM_Base+$7C00 ; Board FPGA Configuration Data Adrs MSA4_BA EQU FM_Base+$1000 ; Base addres of MSA4 FPGA MSA4_Status EQU FM_Base+$1010 ; Control Status Register for MSA4 ; Read Only MSA4 Register #8 MSA4_LE_Ctrl EQU FM_Base+$1016 ; Control Register for the Line ; Enable Control Block. Selects ; the number of ADC Clk before LE ; is asserted and the number ; during LE's assertion. ; MSA4 Register #11 MSA4_Frm_Start EQU FM_Base+$101C ; MSA4 Register #14 MSA4_Frm_Stop EQU FM_Base+$1022 ; MSA4 Register #17 BSF_BA EQU FM_Base+$4400 ; Base addres of BSF FPGA BSF_GlbIO_CSR EQU FM_Base+$4410 ; BSF FM Global I/O plus Control ; Status Register BSF Register #8 BSF_MClk_Phase EQU FM_Base+$4416 ; BSF Register that controls the phase ; of the Master Clk WRT the ADC Clk ; BSF Register #11 BSF_Start_ADC EQU FM_Base+$441C ; BSF Register that controls the ; number of Raw ADC Clk pulses ; between Integrate falling and ; sending ADC Clk to the Camera. ; BSF Register #14 ; Typical value ~ 409 = $0199 BSF_Stop_ADC EQU FM_Base+$4422 ; BSF Register that controls the ; number of ADC Clk pulses sent to ; the Camera. BSF Register #17 ; Typical value ~ 17,819 = $459B ; or is it 17,822 BA_68k_Code EQU $00010000 ; Base Address of 68k program BA_MSA4_Code EQU $00040000 ; Base Address of MSA4's Configuration BA_BSF_Code EQU $00060000 ; Base Address of BSF's Configuration ************************************************************************* * Define Constants: * * * * Specify the symbols to Import. * ************************************************************************* XREF ChrStrgOut ; Symbols defined XREF ChrWrtOut ; in other modules XREF BinASCII ; and used in this ; module. END