Package and Power Supplies: --------------------------- 1. What type of package does the TCM2620 come in ? From the information that I have, I can tell that it has 68 pins and I can guess that it is a leadless chip carrier. Do you have a recommended socket for low temperature use with this device ? 1. It is a 68 pin carrier with plated side and bottom contacts. We use a side contact socket. The numbers and letters on the box are AMP, FMT 995162-1, and PN 641749-2-00. Others use a bottom contact, zero insertion force socket TEXTOOL 268-4963. Both must be modified to allow dewar coldfinger to contact back of carrier. 2. From the data sheet I understand that the pins named: VDD, COLHI, AMPHI, and ABAMPHI are all power supply pins to this device. Is there any required sequence in applying these supply voltages that needs to be followed ? Are external protection diodes needed to insure that one supply is not applied without the others ? 2. The chip has protection diodes on it and we don't worry about sequencing the biases and clocks. We ground ourselves when handling and don't power the socket during installation of the device. 3. On the analog side I see three analog power supply pins (COLHI, AMPHI, and ABAMPHI) but only two analog return pins (COLLO and MUXSUB). Is this understanding correct ? 3. Yes. See 8. Below. 4. There are three external analog control voltages that are applied to this device: DSUB, VCLAMP, and MIRROR. Is there any rule about the sequence in which these control supplies are applied to the device ? 4. No rules. 5. For optimum performance of this device do you recommend separate power supplies for some of the sections, e.g. one supply for VDD and another supply for the analog sections ? 5. We wire our dewars with separate supplies but common returns. 6. Do you have a recommended ground plane - power plane layout for use with this device ? 6. We have a general purpose 4" square circuit board with the AMP socket at the center and a ground plane on one side with array of feedthru holes on 0.1 inch centers. We run hookup wire from socket pins to the board's edge connecctor contacts. It is not optimized. 7. Are there recommendations for power supply by pass capacitors for use in the dewar up close to this device ? 7. The Page 3 DC Cable chart has a column for TEST Dewar Filtering which specifies a 4.7 mF polarized capacitor for low speed filtering and a 0.1 mF ceramic disk capacitor for high speed. On low current bias lines, series resistors can be used. 8. In the last row of the "DC Cable" table on page #2 it lists a signal named "ABAMPLO". I do not find a pin for this signal or see any other mention of ABAMPLO anywhere. 8. The GND and ABAMPLO entries are erroneous. There should be a VSS entry her for the digital return. 9. The table "TCM2620" on page #3 lists 37 signals but the table on pages #6 and #7 "TCM2620 Interface" lists only 36 signals. The signal named TCOLRSTB on page #3 does not appear in the table on pages #6 and #7. Also in the table on page #3 no function is listed for the TCOLRSTB signal. Is there anything special about the TCOLRSTB signal ? Do we need to handle it in some special way ? 9. There are many digital testpoint outputs that the designer put there to debug his circuit in case it didn't operate as expected. Leave them floating, and don't worry about them. Analog Video Signal Outputs: ---------------------------- 10. How much can I load the analog outputs both in terms of resistance and capacitance ? Typically for high accuracy high frequency signal processing one tries to keep the resistances low but I can well imagine that you do not want to source or sink much current at the outputs of this device. 10. We run this output into a high impedance preamp and load it with enough capacitance to limit the bandwidth to what's needed at the chosen clock rate. 11. From the data sheet I understand that the analog output video signal excursion will be on the order 2.4 Volts but I do not understand what the "baseline output voltage" will be (i.e. the output voltage that occurs during readout when the device has collected no IR photons). Is this the same as the analog output voltage during "dead times", which I understand to be controlled by the VCLAMP input control voltage ? From your data sheet I took "dead times" to mean when the device is not reading out. Or is the "baseline output voltage" equal to the dead time output voltage minus 1/2 of the video signal excursion ? 11. My data show 3.1 V at zero signal and 1.3 V at saturation.. These levels depend on some of the analog biases. The designer who created the page 5 claiming 2.4V range probably tweaked the biases to get the extra range. VCLMP sets the output level during the period between row scans and between frames. 12. From the data sheet I understand that the pins named: COLLO, and MUXSUB are both analog power supply "return" lines. I did not understand which one of these analog returns the analog outputs are referenced to. Is it COLLO ? 12. We set both at 0V and reference to that level. Monitoring and Testing: ----------------------- 13. Can you explain how we could use the TEMP1 and TEMP2 pins to monitor the temperature of the device ? 13. The resistance between these to pads is strongly temperature dependent. Calibrate in your dewar with no thermal load on the FPA package by reading the dewar coldfinger temperature with a factory calibrated diode thermometer. 14. Which of the analog test pins (CASCODE, COLLBIASP, COLBIASN, CELLBIAS, COLBIAS, and SLOWBIAS) should we monitor ? What are the conversion factors to go from the external voltage that we would measure to the internal parameter that is being monitored ? What is the acceptable range for the values of these different parameters ? 14. These are not test pins. The are bias inputs used to override the autobias circuitry. Float the pins to use the default biases. I had to override only COLBIASN at 1.35V to get the different amplifier stages lined up. Some tweaking is necessary to maximize dynamic range for each application. 15. The data sheet lists 9 Logic Test pins (i.e. TRST, TISHB, TISHRST, FRAMECHK, LINECHK, TVCLK, TFSYNCB, TPHI1, and TPHI2). I assume that these are 5V CMOS logic level outputs. Which of these should we be setup to monitor and what waveforms should we expect to see ? 15. Forget these and just worry about the clock inputs. Adjustments: ____________ From reading the data sheet I believe that the following three control voltages could be adjusted to optimize the performance of the TCM2620: DSUB, Detector Substrate VCLAMP, Voltage sets the output voltage during dead times MIRROR, External current source 50 uAmp 16. What is the function of DSUB and how should we adjust it ? i.e. what parameter are we trying to optimize by adjusting it ? 16. DSUB is the detector substrate connection, the common contact to all detector diodes. It is adjusted to set the reverse bias of the detectors. Resolution should be a few mV. 17. What criterion should be used to set the VCLAMP control voltage ? How does its adjustment effect the performance of the TCM2620. 17. VCLAMP is set to give approximately the output level of the background detector signals so your preamp doesn't have to slew big voltage changes at the beginning of each row scan. You may also measure the noise here to distinguish noise sources up and downstream from the FPA output driver. 18. I do not understand the function of the MIRROR and AUTOBIAS pins. What is this current source supplying current to ? For our use of the TCM2620 can we just ground the AUTOBIAS pin (thus enabling the internal 50 uAmp current source) and obtain optimum performance from the device ? If we use an external current source, over what range should we make it adjustable and what characteristic of the TCM2620 are we optimizing by adjusting this current source ? 18. It should be OK just to use the internal autobias. "Fine tuning" capabilities were designed into this readout circuit to allow users to optimize performance. Different settings are appropriate for different operating temperatures, signal ranges, clock speeds, system noise, etc. You must breadboard and operate the device to determine your requirements before hardwiring your electronics. Operation and Digital Control: ------------------------------ 19. Does the noise of the device vary as a function of the CLOCK frequency ? 19. Yes. Much of this is external to the device due to clock pickup. It's often difficult to pinpoint the causes. As mentioned in 10 above, you should limit your bandwidth to the minimum required. 20. For long integration time is there any advantage in stopping the CLOCK signal ? 20. We have no experience here. Try it and see. 21. In the timing diagram transitions of the INTEGRATE signal are shown coincident with positive edges on the CLOCK signal. But the text says nothing about the required relative timing of these two signals. When should INTEGRATE make transitions relative to the CLOCK. 21. We clock it as drawn without worrying about the details. At some high clock speed I would expect to have to optimize delays. We haven't characterized such effects because other things (like ADC effects) stop us before we get to such high speeds. 22. In the notes below the timing diagram it says that INTEGRATE signal may be taken high again "after data appears at the output". Does this mean that the device must finish reading out before INTEGRATE may be taken high again or does it mean that INTEGRATE may be taken high again as soon as the analog output data for the first pixel appears at the analog output ? i.e. Can the device integrate photons and readout at the same time ? 22. Yes, you may begin integrating while the previous integration is being read out. 23. At the end of the photon integration period the integrated data is sampled in a process that requires either 10 usec or 100 usec (as selected by the MODE control signal). The timing diagram shows that from the falling edge of the INTEGRATE signal until the analog data first begins to come out of the device there is a delay of either 71 CLOCK periods (for a 10 usec sampling time) or 207 CLOCK periods (for a 100 usec sampling time). Trying to put all of this information together to understand how the device operates, it appears that the interval from the falling edge of the INTEGRATE signal until analog output data first begins to appear consists of a sampling period (that lasts for either 15 CLOCK cycles or 150 CLOCK cycles) plus a MODE independent fixed delay of about 57 CLOCK cycles. Is this how the device operates ? When you state the sampling period in usec you must have been making an assumption about the CLOCK frequency. If my understanding above is correct then it appears that you were operating the device with a 1.5 MHz CLOCK, i.e. 3 mega pixels per second per analog output. Is this correct ? Is this an optimum operating CLOCK frequency ? 23. I operate and test devices like this without ever looking at the circuit schematics. I would love to understand the internal workings but don't have the time. I use a programmable waveform generator to create the clock signals. When I get a new readout, I program extra clocks/row and extra rows/frame to make sure all the overhead functions that require extra clocks are performed. It never hurts to overclock. It just adds to the dead video time between rows and frames. The output waveform displayed on the oscilloscope is then monitored as you cut down the number of clocks. Eventually the circuit stops working. There is no optimum clock frequency in general. Often the accuracy of the ADC (12, 14, 16 bit) determines the maximum clock frequency. Clearly, it takes more work to get control of system generated noise at high frequency. At low frame rates, bias and temperature stability can become limitations.