Initial Implementation of Fast IR Camera THE-Card Logic --------------------------------------------------------- Initial Rev. 22-MAY-1997 Current Rev. 11-JAN-1998 3-MAR-2001 rework the section that describes using the 68k to configure the FPGA's Operation Setup of the TCM-2620: -------------------------------- Select the Integration Capacitor (either 10.7 fF or 101.9 fF) by pulling pin #37, CapBSwB, either voltage high -> 10.7 fF or low -> 101.9 fF. Select the Input Sample/Hold time (either 10 usec or 100 usec) by pulling pin #64, Mode, either voltage high -> 10 usec or low -> 100 usec. Select the internal or external current source for the bias generator by setting pin #45, AutoBias, voltage low -> internal or floating it to select the external current source . If an external current source has been selected for the bias generator (by floating AutoBias pin #45) then supply this current via the Mirror pin #46. If using the internal current source then float the Mirror pin. Set the Detector Substrate Voltage, pin #38, DSub. This is in the range 3.5 to 4 Volts. Set the output voltage during "dead time" via pin #55, VClamp. This is in the range 1 to 4 Volts. This is called the VClamp supply. 1. My current guess is that permanently running from the internal current source for the bias generator is OK. Thus permanently grounding AutoBias and permanently floating Mirror is OK 2. If the above understand is correct then only the Digital Control inputs are: CapBSwB and Mode and the Analog Control inputs are: DSUB and VClamp. First Test Digital Setup ------------------------ The TCM-2620 will run with a 0.5 MHz Master Clock. Thus it will produce a new pixel from each of the quadrants every 1 usec. Thus the ADC's will run with a 1 MHz clock. The pixel clock rate going back to the host computer will thus be 4 MHz, i.e. a new pixel every 250 nsec. The phase shift between the 0.5 MHz TCM-2620 master clock and the 1 MHz ADC Clock will need to be adjustable so that the TCM-2620's analog pixel signal has time to propagate through the analog processor and settle in the ADC's track and hold before the ADC conversion cycle is started. |<--------- 2 usec -------->| | |<- 1 usec -->| TCM-2620 +-------------+ +-------------+ +----- Master ^ v ^ v ^ Clock --+ +-------------+ +-------------+ | | | | | TCM-2620 Analog dddddeeeeeeeeeeeeeeffffffffffffffgggggggggggggghhhhhhhhhhhhhhiii Output | | | | | Analog Processor ddddddeeeeeeeeeeeeeeffffffffffffffgggggggggggggghhhhhhhhhhhhhhii Output | | | | | --+ +---+ +---+ +---+ +---+ ADC | ^ | ^ | ^ | ^ | Clock +---------+ +---------+ +---------+ +---------+ +----- | | | | | ---+ +---+ +---+ +---+ +---+ ADC | ^ | ^ | ^ | ^ | EOC* +---------+ +---------+ +---------+ +---------+ +---- | | | | | ADC Digital c...ddddddddddd...eeeeeeeeeee...fffffffffff...ggggggggggg...hhhh Output | | | | | |<- 1 usec -->| Notes: The TCM-2620 "documentation" shows that the analog output information changes coincident with the TCM-2620 Master Clock edges. How much delay there is in this is not known. The delay through the analog processing will be order of 75 nsec to 1 usec i.e. an indeterminate fraction of the pixel time (500 nsec) The Summer 1997 version of the A-Card Analog Processor, the 1 MHz version, has the following characteristics for a step function input: Delay from Input to: Output begins to move 100 nsec Output 1st crosses final value 800 nsec Output reaches peak value 960 nsec Output "is at" final value 1450 nsec The ADC switches from track to hold about 10 nsec after the rising edge of the ADC Clock. Thus the rising edge of the ADC Clock should occur near the end of the period that the output from the Analog Processor is stable for a given pixel. In this slow initial test having the ADC Clock positive edge occur 50 to 100 nsec before the Analog Processor output starts to move to its new value for the next pixel should be fine. All ADC activity is timed from the rising edge of its clock. In this slow initial setup we purposely keep the ADC clock high for about 125 nsec so that the falling edge of the ADC clock does not occur during the actual conversion process. The ADC digital output for ADC conversion "N" remains valid for about at least 40 nsec after EOC* goes invalid (high) for conversion "N+1". Initial Implementation ---------------------- For the initial implementation the idea is to continuously deliver TCM-2620 Master Clock. Either an AIA Mode Signal or the 68K generates the Integrate signal. THE-Card logic updates the Integrate signal going to the TCM-2620 only on rising edges of the TCM-2620 Master Clock. For analog readout, each Row requires 64 TCM-2620 Master Clock Edges i.e. 32 TCM-2620 Master Clock cycles. The first pixel of analog readout data begins appears following a falling edge of the TCM-2620 Master Clock. Between Rows there are 4 TCM-2620 Master Clock edges with no pixel data. There are 33, 71, 173, or is it 207 falling edges of the TCM-2620 Master Clock between Integrate coming back low and the first pixel of analog readout data appearing. Integrate may go high again, to begin collecting frame "N+1", as soon as the first analog output data for frame "N" begins to appear at the TCM-2620's outputs. What we need to know from AIA A15.08/3 --------------------------------------- The Pixel_Clock must run continuously while the Line_Enable signal is active (voltage high). The Pixel_Clock must make at least one positive edge before Line_Enable becomes active and it must make at least on positive edge before Line_Enable returns to inactive. (-> Pixel Clock may/must run continuously ?) The Frame_Enable goes active (voltage high) at the beginning of a frame, e.g. at the same time a Line_Enable goes active for the first line in the frame. Frame_Enable remains continuously active for the full duration of the frame. Frame_Enable returns inactive at (or after) the conclusion of the last line in the frame. All signals (Data, Line_Enable, Frame_Enable) have the same setup and hold time requirements. These are measured with respect to the positive edge of the Pixel_Clock. The specification is: setup min 25 nsec, hold min 15 nsec. Timing Signal Labels -------------------- There are a number of different labelings used for the Timing Signals in this THE-Card - Camera chain. In some places the labels begin with 0 and in other places with 1. Another confusing point is that in the THE-Card FM world, timing signal means the signals that come in the top of the backplane P1 connection; where as in the world of this project timing signal can also mean the signals that are generated by the FM's Board Support Functions FPGA and sent out to the Camera on the FM's Global I/O connector. From FM THE-Card the Camera Timing Signals emerge on the P5 Global IO connector. These signals on the FM card are labeled Glb_IO_(0:16). The Glb_IO_(0:16) signals will be organized for the FIRC project in the following way. The lower 8 Camera Timing Signals are generated by logic and the upper 8 Camera Timing Signals are generated from a VME programmable RW register. The "17th Signal" comming off of the THE-Card Global Connector will not be used. Glb_IO_(0:7) Glb_IO_(8:15) Glb_IO_16 ------------ ----------------- ------------ From Clocked From Programmable Driven by FM Logic on FM Register on FM but not used by the FIRC Initial Implementation of the Timing Signals -------------------------------------------- Camera Timing Signals from the FM Board are numbered Glb_IO_0 through Glb_IO_16. In the FIRC Camera Logic these same signals are often called TS_0 through TS_16 or even TS_1 through TS_17. Glb_IO_0 through Glb_IO_7 are generated by logic on the Board Support Functions FPGA. These signals are assigned the following functions: D-Card Label and Pins FM Label ---------------------------- Function and P5 Pins Label Pins IN Pins Out ---------------------------- ------------ ---------------------------- driven low Glb_0 1-2 TS_1 1-2 dead end Camera ADC Clock Glb_1 3-4 TS_2 3-4 ADC Clk driven low Glb_2 5-6 TS_3 5-6 31-32 Camera TCM-2620 Master Clock Glb_3 7-8 TS_4 7-8 29-30 driven low Glb_4 9-10 TS_5 9-10 27-28 Camera TCM-2620 Integrate Glb_5 11-12 TS_6 11-12 25-26 driven low Glb_6 13-14 TS_7 13-14 23-24 driven low Glb_7 15-16 TS_8 15-16 21-22 Glb_IO_8 through Glb_IO_15 originate in bits D8:D15 of a register on the Board Support Functions FPGA that the 68K can load and read. When the 68k writes a "1" to one of these bits, the corresponding Camera Timing Signal is set active (voltage high). D-Card Label and Pins FM Label ----------------------------- Function and P5 Pins Label Pins IN Pins Out ---------------------- -------------- ----------------------------- driven low Glb_8 17-18 TS_9 17-18 19-20 Camera TCM-2620 Mode Glb_9 19-20 TS_10 19-20 17-18 driven low Glb_10 21-22 TS_11 21-22 15-16 Camera TCM-2620 CapSwB Glb_11 23-24 TS_12 23-24 13-14 driven low Glb_12 25-26 TS_13 25-26 11-12 driven low Glb_13 27-28 TS_14 27-28 9-10 driven low Glb_14 29-30 TS_15 29-30 7-8 driven low Glb_15 31-32 TS_16 31-32 5-6 Note that when used with this setup the D-Card needs a small ECO to move the ADC_Clk form D-Card TS_1 (FM Glb_0) to D-Card TS_2 (FM Glb_1). This is done by cutting two traces at their via bridges in front of U6. Cut the U3 P24 bridge trace to U6 P5. Cut the U3 P23 bridge trace to U6 P6,P7,P8,P9. Connect the bridge U3 P24 to U6 P6,P7,P8,P9. Connect U6 P5 to GND. Leave open U3 P23. Foundation Module Block Diagram and Details ------------------------------------------- T.S. VME MSA_IN 0:63 MSA_IN 64:127 +-----------------+ +-----------------+ +-----------------+ +--| P1 |---| P2 |---| P3 |--+ | +-----------------+ +-----------------+ +-----------------+ | | +-----+ | | | # 0 | +-----+ +-----+ +-----+ +-----+ | | +-----+ | # 1 | | | | | | # 4 | | | VME +-----+ +-----+ +-----+ +-----+ | | | | +-----+ +-----+ +-----+ +-----+ +-----+ | | | # 17| | | | | | | | | | | +-----+ +-----+ +-----+ +-----+ +-----+ | | Brd Support Main Signal Processing Array | | Functions +-----+ +-----+ +-----+ +-----+ | | | | | | | | | | | | +-----+ +-----+ +-----+ +-----+ | | | | +-----+ +-----+ +-----+ +-----+ | | | # 13| | | | | | # 16| | | +-----+ +-----+ +-----+ +-----+ | | +----------+ +-----------------+ | +------------------| P5 |---------| P4 |---------+ +----------+ +-----------------+ MSA_OUT 0:63 The mapping of MSA_IN and MSA_OUT signals to the four chips in the FM's Main Signal Processing Array is: Chip Reference Number Designator MSA_IN MSA_OUT ------ ---------- ------------------------ ---------------- 1 U52 MSA_IN 0:127 MSA_OUT 56:59 4 U53 MSA_IN 0:63 MSA_OUT 0:31 13 U54 MSA_IN 64:127 MSA_OUT 32:55 14 U55 MSA_IN 64:71 MSA_OUT 60:63 14 loads on MSA_IN_80 MSA_IN 88,89 MSA_IN 96:100 MSA_IN 104:107 14 loads on MSA_IN_108 14 loads on MSA_IN_109 14 loads on MSA_IN_110 14 loads on MSA_IN_111 Foundation Module: Timing Signal Details, Global I/O Details Initial Implementation THE-Card Registers Viewable from the 68K --------------------------------------------------------------- Let's pick Slot Number #22 for the FM Card in the Fast IR Camera. The card in Slot #22 has a Base Address of $0011 0000. We need a base address above $0010 0000 in order to allow the MVME-133 to have direct VME access to the card. /\/\/\/\/\/\/\/\/\/\\/\/\/\/\//\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\ MSA #4 Registers Using a card base address of $0011 0000 puts this card's MSA #4 FPGA at a base address of $0011 1000. In the following, Number are in decimal unless marked with a $ for base 16. Register Number #8 VME Adrs $0011 1010 is Control Status Register for MSA #4. It is a 16 bit register. The bits are assigned in the following way: Read Bit Bit Write Group Function Value --- ----- ----- -------------------------- ------- 0 Rd Frame Enable 1 1 Rd S Line Enable 2 2 Rd T Delivering Data 4 3 Rd A nc 8 4 Rd T Enable ADC Mux #1 16 5 Rd U Enable ADC Mux #2 32 6 Rd S Enable ADC Mux #3 64 7 Rd Enable ADC Mux #4 128 8 R/W C nc 256 9 R/W O nc 512 10 R/W N nc 1024 11 R/W T nc 2048 12 R/W R nc 4096 13 R/W O nc 8192 14 R/W L nc 16384 15 R/W nc 32768 All signal are in their active state when set at logical 1 MSA #4 Register Number #11 VME Adrs $0011 1016 is the control register in the Line Enable Control block. This register allows on to pick the number of ADC cycles before the Line Enable signal becomes active and then the number of ADC cycles before the Line Enable signal returns low. All 16 bits are Read-Write bits. They are used in the following way: Bit: D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 ------------------------------- ------------------------------- Number of ADC Cycles Number of ADC Cycles before the Line Enable before the Line Enable Returns Low. Becomes Active. Typical Value is 66 Typical Value is 2 So the value loaded would be (66 x 256) + 2 = 16898 = $4202 Register Number #14 VME Adrs $0011 101C is the Start Frame Enable Count register in MSA #4. It is a 16 bit register. The is the count of the number of Quad Done pulses before Frame Enable becomes active at the beginning of each frame. Typical value loaded is 1. Register Number #17 VME Adrs $0011 1022 is the End Frame Enable Count register in MSA #4. It is a 16 bit register. This is the count of the number of Quad Done pulses before Frame Enable returns un-asserted at the end of each frame. Typical value is order of 68x256 = 17,408. Currently the value 17,407 = $43FF is actually used. /\/\/\/\/\/\/\/\/\/\\/\/\/\/\//\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\ BSF Registers Using a card base address of $0011 0000 puts this card's BSF (Chip Number #17) at a base address of $0011 4400. In the following, Number are in decimal unless marked with a $ for base 16. BSF Register Number #8 VME Adrs $0011 4410 is the Global I/O Plus Control Status Register. It is a 16 bit register. The bits are assigned in the following way: Read Bit Write Group Function Bit Value --- ----- ----- -------------------------- ------------------ 0 Rd Integrating 1 $0001 1 Rd S Doing Readout 2 $0002 2 Rd T ADC Clock ON 4 $0003 3 Rd A ECO AND 8 $0008 4 Rd T EOC OR 16 $0010 5 Rd U nc 32 $0020 6 Rd S nc 64 $0040 7 Rd nc 128 $0080 8 R/W G nc 256 $0100 9 R/W l Array Mode 512 $0200 10 R/W b nc 1024 $0400 11 R/W I-O Array CapSwB 2048 $0800 12 R/W C Integrate Control 4096 $1000 13 R/W t External Integrate Enable 8192 $2000 14 R/W r nc 16384 $4000 15 R/W l Force ADC Clock to Run 32768 $8000 All signal are in their active state when set at logical 1 BSF Register Number #11 VME Adrs $0011 4416 is the control register in the Clock Generator Module. It picks the phase relationship between the Master Array Clock and the ADC Clock. This register picks the "begin pulse" and "end pulse" addresses for the Master Array Clock. All 16 bits are Read-Write bits. They are used in the following way: Bit: D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 ----------- ------------------- ----------- ------------------- Must be Counter Value at Must be Counter Value at Zero which to END the Zero which to START the Master Array Master Array Clcok Pulse Clcok Pulse Typlical Value Typical Value Loaded 16:31 Loaded 0:15 Master Array Degrs Clock Counter Wait in nsec from ADC Clk -------------- Master Array Clock Phase Start End Edge to Next ADC Shift Value Value Register Value Clock Rising Edge ----- ----- ----- --------------- ----------------------- 0 0 16 4096 $1000 0.0 (or 1000) nsec 22.5 1 17 4353 $1101 937.5 45.0 2 18 4610 $1202 875.0 67.5 3 19 4867 $1303 812.5 90.0 4 20 5124 $1404 750.0 112.5 5 21 5381 $1505 687.5 135.0 6 22 5638 $1606 625.0 157.5 7 23 5895 $1707 562.5 180.0 8 24 6152 $1808 500.0 202.5 9 25 6409 $1909 437.5 225.0 10 26 6666 $1A0A 375.0 247.5 11 27 6923 $1B0B 312.5 270.0 12 28 7180 $1C0C 250.0 292.5 13 29 7437 $1D0D 187.5 315.0 14 30 7694 $1E0E 125.0 337.5 15 31 7951 $1F0F 62.5 BSF Register Number #14 VME Adrs $0011 441C is the Start ADC Clock Train Register. Typical value ~ 410 = $019A BSF Register Number #17 VME Adrs $0011 4422 is the Stop ADC Clock Train Register. Typical value ~ 17,820 = $459C i.e. Readout in 17.6 msec. /\/\/\/\/\/\/\/\/\/\\/\/\/\/\//\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\ Discussion of the values loaded into the BSF Registers. BSF Register Adrs 11 Master Array Clock Phase Shift For now we will do all of the testing using decimal 4353 in this register. This gives a long wait until the ADC Clock pulse and it has the previous ADC Clock edge just before a Master Array Clock edge. The only place where thinking about the logic gets tricky is when the ADC Clock edge is just after the Master Array Clock edge. BSF Register Number #14 Start ADC Clock Train Register BSF Register Number #17 Stop ADC Clock Train Register The 207th falling edge of the Master Array Clock after the Integrate Signal falls is the beginning of the first Pixel coming out of the TCM-2620. This would be the 413 ADC Clock pulse after Integrate falls. But we need the 411th and 412th Raw ADC Clock pulses to also go to the camera. So if immediately after the 409th positive Raw ADC Clock edge the Comparator goes True then this will make it through the comparator's latch on the 410th positive edge of the Raw ADC Clock and the ADC Clock gate will go True at the falling edge of the 410 Raw ADC Clock pulse which will let the complete 411th Raw ADC Clock pulse flow through to the Camera. So, we need to set the Start ADC Clock Train Register comparator value to 409. This is about right. So the first pixel is on the 413rd ADC Clock Pulse and then you need 256x68 = 17,408 ADC Clock pulses to get all the data out. Note that this is really 256x64 + 255x4 = 17,404 to get the data out but then you need an extra 4 on the end to complete the run down of the readout engine which gets you back to 17,408. But the comparator value that you want to look for for the Stop Clock Train Register is 2 less than this; one less because of pipeline and one less because of phase relationship. So the value that you want is: 412 + 17,408 - 2 = 17,822. Note that 412 was used, not 413, because pulse 413 is also the first pulse in the series of 17,404 required to get the data out of the chip. This is about right. /\/\/\/\/\/\/\/\/\/\\/\/\/\/\//\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\ Connection to the EDT Card The EDT Card uses DS26C31 and DS26C32 chips for its RS422 receiving and sending. We need to connect on of these output to the Backplane TS #7 input to receive the Mode-0 signal which will be used as the External Integrate signal. Basic Specs: DS26C31 Line Driver Typical Outputs: Low +0.3 High +3.4 Volts Min/Max Outputs: Low +0.5 High +2.5 Volts DS26C32 Line Receiver Common Mode Range +- 7 Volts Minimum Differential Input 200 mV The 300k ECL inputs to the 100325 are: -1830 to -1475 -1320 -1165 to -870 mV ---------------- ------- ---------------- Low typ -1720 Vbb High typ -920 The differential ECL outputs from THE_Card FM Modules should be able to directly drive the DS26C32 Line Receiver Inputs. Positive RS-422 to normal ECL shift circuit. Clamp the positive RS-422 signals to not swing below Gnd. Pass these signals through 1k Ohm resistors and then through 270 Ohm resistors to -2.0 Volt Vtt. At the junction of the 1k's and 270's clamp to not swing positive wrt Gnd. This junction provides the normal differential ECL signal. /\/\/\/\/\/\/\/\/\/\\/\/\/\/\//\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\ PROBLEMS Connecting to the EDT Card The EDT card says RS-422 but it does not allow any negative input voltages because the 26C31 Drivers that are on each signal clamp the signals to not swinging under Gnd. Solution, remove 5 of these drivers (from the 16 Data lines and the Pixel Clk, Frame Enb, and Line Enb lines). EDT card says AIA but it requires that pixel clock run outside of the asserted Frame Enable signal period. Solution, add a Frame Enable Control Block to MSA4 that asserts Frame Enable only after 4 pixel clocks at the beginning of each frame and that drops Frame Enable while there are still 4 pixel clocks to go at the end of each frame. Third problem. The SUN software is setup so that The integrate signal does not appear on the Mode 0 lines, MC0, as expected but rather it is on FRMRST/EXP, i.e. pins 78 and 79. Forth problem. It appears that EDT has numbered their data inputs so that D0 is the MSB and D15 is the LSB. This is not in the AIA spec. So we flip the signals in out data cable. Fifth problem. It appears that either EDT or Fritz is using the most significant 14 bits of the 16 (i.e. in EDT parlance D0 (MSB) through D13 the next to the next LSB). So we shift the FM card data by 2 bits. /\/\/\/\/\/\/\/\/\/\\/\/\/\/\//\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\ How to use the MVME-133 68k processor module to "Configure" the FPGA's in the FIRC's VME Digital Logic Board and to load the various control registers with their proper values. --------------------------------------------------------------- The digital logic for the FIRC is all located on an FM card (Foundation Module) in the 9U VME card file. The logic is implemented with Xilinx 4000 series FPGA's. These FPGA's forget everything when their power is turned off. Xilinx calls the process of putting the logic design into the FPGA "configuring" the FPGA. So every time the FIRC is powered up the first thing that needs to happen is to configure the FPGA's that are used to implement its logic. The FM card is designed to receive the configuration data for its FPGA's from the VME backplane. A Motorola 68k CPU module is used to generate the VME cycles that send the configutation data over the VME backplane to the FM card. A small program called "x_loader" runs on the 68k to generate these VME cycles and thus accomplish configuring the FPGA's. Three files, stored on the host SUN, are first moved from the SUN into the 68k's onboard memory space and then used to configure the FPGA's. These files are: x_loader.abs S9 recoreds of the 68k x_loader executable firc_msa4_102.abs Configuration data for the "Main Signal Array #4" FPGA stored as S9 records. firc_bsf_103.abs Configuration data for the "Board Support Function" FPGA stored as S9 records. The 68k contains an onboard "BUG Monitor" EPROM program that is used to read in over a serial port the S9 records and store their contents at the appropriate onboard memory locations. The x_loader.abs S9 file contains all the appropriate information so that the BUG Monitor knows where to store this executable in the 68k's onboard memory. The firc_msa4_102.abs and firc_bsf_103.abs S9 files internally indicate a starting address of zero. When we load these two files we will explicitely tell the BUG Monitor where to store them in 68k's onboard memory. We use the tip program on the SUN both as a "terminal emulator" to communicate with the 68k BUG Monitor and to output the S9 files over the serial link from the SUN to the 68k. Start up the tip program using: > tip -9600 /dev/ttyb # assuming SUN serial port B Typing return at this point will send a "carriage return" character to the 68k BUG Monitor and it will echo "Bug133>" indicating that it is ready to receive a command. The first BUG Monitor command that we will use is the "LOad 0 $xxxx". This means "load" S9 records received from serial port ZERO starting at address offset $xxxx from the start address contained in the S9 records. We will use the BUG Monitor Load command 3 time to load the 3 files. The sequence is: (cr) = "carriage return" Bug133> LO 0 (cr) # 68k, get ready to receive S9 records and # store them at the address they indicated. "tilda greater-than" x_loader.abs (cr) # tip, send out the file # x_loader.abs Bug133> LO 0 $40000 (cr) # 68k, get ready to receive S9 records and # store them at the address offset $40000. "tilda greater-than" firc_msa4_102.abs (cr) # tip, send out the file # firc_msa4_102.abs Bug133> LO 0 $60000 (cr) # 68k, get ready to receive S9 records and # store them at the address offset $60000. "tilda greater-than" firc_bsf_103.abs (cr) # tip, send out the file # firc_bsf_103.abs The serial link with the 68k is 9600 baud or about 1000 characters per second. So from the size of the file you can get an idea of how long each file transfer will take. After all 3 files are loaded into the 68k's memory the next step is to run the x_loader program. We start this program by telling the BUG Monitor to transfer execution from itself to some starting address. The starting address that we want to use is $10000. The BUG Monitor command to make this happen is: Bug133> go $10000 (cr) The x_loader program will now take over the 68k and it will report its progress configuring the FPGA's by sending messages out the 68k's serial port which tip will display. While it is using the VME bus to send configuration data to the FM card you will see two LED's flash on the card in slot #2 (the TOM card that holds the 6U Motolola 68k VME card and plugs it into the 9U card file). When x_loader conpletes configuring the FPGA's (about 5 or 10 seconds) it will report the values contained in a couple of registers that let you verify that the FPGA's have been configured and that they "woke up" and are implementing the desired logic. X_loaded then completes this section by advertize 3 additional starting addresses in the x_loader program and then it exits back to the BUG Monitor. You need to use one of these additional starting points in the x_loader program to load default values into the various control registers that now exist in the FPGA's (now that they are configured). All of these control registers are by design "visible" to the VME Bus so the 68k just does more VME cycles to load values into them. This entry point for this is at address $12000 so: Bug133> go $12000 (cr) This loads a number of control registers and reports the values that have been loaded and exits back to the BUG Monitor. The other two sections in the x_loader program are at $14000 to display the values in the various control registers and at $16000 to generate a short "integrate signal" to the camera for testing. You would use them in the following ways. If you wanted to change the value in one of the control registers you just need to get the 68k to do a write cycle to the proper address (remember all the control registers are visible from VME) with the data value that you want. Reading the documentation for the MSA4 and BSF FPGA's will show what address to use and how to understand what the data loaded into each register does. Much of this information is up near the top of this file. You can use the BUG Monitor MM $xxxx command to "modify" i.e. do a VME write cycle to the address $xxxx. Note that a "?" to the BUG Monitor will cause it to display all its possible commands. After changing the value in some control register it would be nice to have a easy way to verify what is actually in all the control registers. That is what you can do by starting the x_loader program at $14000 - it just reads and make a formatted display of the contents of all the control registers. The final section of x_loader starts at $16000 and would be used for testing the camera with out using the EDT card - for example if you just wanted to send data to a logic analyzer of something like that. In the TCM-2620 it is the "intergate" signal that controls the exposure. Termination of the integrate signal cause data to flow out of the TCM-2620 a fixed number of clock cycles later. The x_loader section starting at $16000 asserts the integrate signal for 0.1 sec at a 1 Hz rate. It continues this until you push the abort button on the Motorola 68k module. Note that for all normal operation of the camera the EDT card controls the integrate signal as described above. Below here is the "pre 3-MAR-01" section of this file. -------------------------------------------------------- > tip -9600 /dev/ttyb To send a file first tell the 68k machine to get ready to receive it for example: Bug133> LO 0 # to load x_loader.abs Bug133> LO 0 $40000 # to load firc_msa4_102.abs Bug133> LO 0 $60000 # to load firc_bsf_103.abs This stands for LOad via port #0. The $ sign is the Motorola way of saying base 16. The optional number after LO 0 is the offset that the Load command will add to the "starting addresses" contained in the abs file. Then tell the SUN to send the file. The tip command to send a file is tilda key then greater then key at which point it will prompt you for a file name to send. To exit tip use the tilda key then the control D key. Note that the command to the 68k does not include anything that it needs to send to the host to get the transfer started. Files to send to the VME equipment are: x_loader.abs this abs file includes its proper loading adrs firc_msa4_102.abs load this at $40000 firc_bsf_103.abs load this at $60000 Start the x_loader program running in the VME 68k type the following at the Bug prompt: Bug133> go $10000 After configuring the FPGA's this program will print a message about the starting addresses for additional options. You must run the option at address $12000 which loads up the various control registers in the FPGA logic. /\/\/\/\/\/\/\/\/\/\\/\/\/\/\//\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\ To run the camera display on the Sun: PW c130c130 cd /home/kuhn/ccdidl Message restart Message camera time 25 idl idl> camera r carriage return # to set range of displays To run camera test: cd /opt/EDTsdv # ? this is about right camtest /\/\/\/\/\/\/\/\/\/\\/\/\/\/\//\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\ Jeff Kuhn Home Phone: 517-655-5142 Jeff Sun Spot Lab 505-434-7110 Jeff Sun Spot Office 505-434-7018 Fritz sun spot Office 505-434-7102 EDT general number 503-690-1234 Dan Boer at EDT 503-748-7839