TITLE      I-Source Digital Controller  PAL #1
PATTERN    ISDCPAL1
REVISION   S.03
AUTHOR     none
COMPANY    MSU CMP
DATE       15-MAY-1993

;  The detailed description of this device will be at the end of this file.


CHIP    ISDCPAL1     PAL16RA8


;PINS
; 1        2       3       4       5       6       7        8        9
  /Pre_LD  /PgtQl  /PgtQh  /FrcUp  /FrcDn  /PeqQl  /PeqQh  /PushSwp  EndTrain

; 10
  Gnd

; 11      12       13      14         15           16       17        18  19
 /Glb_OE  DACDir  /DACStb  TrainEnb  /TrainEnbBar  Swping  /StrTrain  In1 Out1

; 20
  Vcc


; This device has active-low outputs.  It simulates programmable
; output polarity by allowing the latch "D" input to be inverted.
; For unlatched outputs, this is equivalent to programmable
; polarity.  For latched outputs, note that SETting the latch
; corresponds to driving the output low, and RESETting the latch
; drives the output high.
;

EQUATIONS

;   /Glb_OE    =    GND                 ; This term is the active-low
;                                       ; Global Output Enable.  By wiring
;                                       ; this term low, all output terms
;                                       ; are controlled by their "per-term"
;                                       ; Output Enable (term.TRST).


;   /Pre_LD    =    Vcc                 ; This term is the active-low
;                                       ; Preload.  By wiring this term
;                                       ; high, the pre-load function is
;                                       ; disabled for all terms.





                                                      ;
/DACDir       :=    FrcDn * /FrcUp
               +   /FrcUp * /FrcDn * /PgtQh * /PgtQl * /PeqQh
               +   /FrcUp * /FrcDn * /PgtQh * /PgtQl *  PeqQh
               +   /FrcUp * /FrcDn * /PgtQh *  PgtQl * /PeqQh

DACDir.CLKF    =    GND
DACDir.TRST    =    Vcc
DACDir.SETF    =    Vcc
DACDir.RSTF    =    Vcc


; Set the DAC-Counter-
; Direction HIGHif we
; are in Force-Up or if
; in Auto and P .GT. Q.
; Note  P is .GT. Q  if
; PgtQh is active or if
; PgtQl is active and
; PeqQh is active.
; P is the Target Code
; Q is current DAC Code




Swping        :=   /PeqQl                     ; Set the Sweeping Flip-Flop on
               +   /PeqQh                     ; the Push-to-Sweep clock only
Swping.CLKF    =    PushSwp                   ; if P is NOT equal to Q
Swping.TRST    =    Vcc                       ; (either the LSB or the MSB).
Swping.RSTF    =    GND                       ; This is really the Set.
Swping.SETF    =    PeqQl * PeqQh * EndTrain  ; This is really the RESET.



DACStb        :=   /Swping * /FrcUp * /FrcDn    ; The DAC is Stable only if we
DACStb.CLKF    =    GND                         ; are NOT Sweeping and we are
DACStb.TRST    =    Vcc                         ; NOT in Force-Up and we are
DACStb.SETF    =    Vcc                         ; NOTin Force-Down.
DACStb.RSTF    =    Vcc                         ;



/TrainEnb     :=    DACStb                    ; Set the Train-Enable on the
                                              ; Start-Train clock only if the
                                              ; DAC is "not stable"  (i.e. only
TrainEnb.CLKF  =    Strtrain                  ; if we are Sweeping or Forcing
TrainEnb.TRST  =    Vcc                       ; Up or Down).
TrainEnb.RSTF  =    GND                       ; This is really the SET.
TrainEnb.SETF  =    EndTrain                  ; This is really the RESET.



TrainEnbBar       :=    TrainEnb              ; Train-Enable-Bar is the
TrainEnbBar.CLKF   =    GND                   ; complement of Train-Enable.
TrainEnbBar.TRST   =    Vcc                   ;
TrainEnbBar.SETF   =    Vcc                   ;
TrainEnbBar.RSTF   =    Vcc                   ;



Out1        :=   /In1                 ; All that we want is a simple inverter.
Out1.CLKF    =    GND                 ;
Out1.TRST    =    Vcc                 ;
Out1.SETF    =    Vcc                 ;
Out1.RSTF    =    Vcc                 ;