// Copyright (C) 1991-2008 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

// PROGRAM		"Quartus II"
// VERSION		"Version 8.1 Build 163 10/28/2008 SJ Web Edition"
// CREATED ON	"Thu Sep 03 12:51:18 2009"

module MyAccum16(
	CK,
	CEN,
	SLD,
	D,
	Q
);


input	CK;
input	CEN;
input	SLD;
input	[15:0] D;
output	[15:0] Q;

wire	SLDN;
reg	[15:0] DFFE_inst12;
wire	[15:0] SYNTHESIZED_WIRE_0;
wire	[15:0] SYNTHESIZED_WIRE_1;
wire	[15:0] SYNTHESIZED_WIRE_2;
wire	[15:0] SYNTHESIZED_WIRE_3;

assign	Q = DFFE_inst12;




MyAdder16	b2v_inst(
	.A(D),
	.B(DFFE_inst12),
	.S(SYNTHESIZED_WIRE_3));


always@(posedge CK)
begin
if (CEN)
	begin
	DFFE_inst12[15:0] = SYNTHESIZED_WIRE_0[15:0];
	end
end

assign	SYNTHESIZED_WIRE_2 = {SLD,SLD,SLD,SLD,SLD,SLD,SLD,SLD,SLD,SLD,SLD,SLD,SLD,SLD,SLD,SLD} & D;

assign	SYNTHESIZED_WIRE_0 = SYNTHESIZED_WIRE_1 | SYNTHESIZED_WIRE_2;

assign	SLDN =  ~SLD;

assign	SYNTHESIZED_WIRE_1 = {SLDN,SLDN,SLDN,SLDN,SLDN,SLDN,SLDN,SLDN,SLDN,SLDN,SLDN,SLDN,SLDN,SLDN,SLDN,SLDN} & SYNTHESIZED_WIRE_3;


endmodule