CMX_generic_spy_mem_control_FSM Entity Reference

Inheritance diagram for CMX_generic_spy_mem_control_FSM:

Entities
multi_seg	architecture

Libraries
IEEE
UNISIM
work

Use Clauses
IEEE.STD_LOGIC_1164.all
IEEE.NUMERIC_STD.all
IEEE.MATH_REAL.all
UNISIM.VComponents.all
work.CMXpackage.all
work.CMX_VME_defs.all

Generics
ADDR_REG_RW_GENERIC_SPY_MEM_WORD	integer := 0
ADDR_REG_RW_GENERIC_SPY_MEM_CONTROL	integer := 0
ADDR_REG_RO_GENERIC_SPY_MEM_STATUS	integer := 0
num_external_RAMS	positive := 1

Ports
clk	in std_logic
ncs	in std_logic
rd_nwr	in std_logic
ds	in std_logic
addr_vme	in std_logic_vector ( 15 downto 0 )
data_vme_in	in std_logic_vector ( 15 downto 0 )
data_vme_out	out std_logic_vector ( 15 downto 0 )
bus_drive	out std_logic
mode_control	out std_logic_vector ( 3 downto 0 )
ena	out std_logic
wea	out std_logic
addra	out std_logic_vector ( 7 downto 0 )
mem_select_address	out std_logic_vector ( addr_port_width ( num_external_RAMS ) - 1 downto 0 )
dina	out std_logic_vector
douta	in std_logic_vector
port_b_master_inhibit	out std_logic

Detailed Description

Definition at line 23 of file CMX_generic_module_spy_mem_control_FSM.vhd.

Member Data Documentation

ADDR_REG_RO_GENERIC_SPY_MEM_STATUS integer := 0

Generic

Definition at line 27 of file CMX_generic_module_spy_mem_control_FSM.vhd.

ADDR_REG_RW_GENERIC_SPY_MEM_CONTROL integer := 0

Generic

Definition at line 26 of file CMX_generic_module_spy_mem_control_FSM.vhd.

ADDR_REG_RW_GENERIC_SPY_MEM_WORD integer := 0

Generic

Definition at line 25 of file CMX_generic_module_spy_mem_control_FSM.vhd.

addr_vme in std_logic_vector ( 15 downto 0 )

Port

Definition at line 38 of file CMX_generic_module_spy_mem_control_FSM.vhd.

addra out std_logic_vector ( 7 downto 0 )

Port

Definition at line 58 of file CMX_generic_module_spy_mem_control_FSM.vhd.

bus_drive out std_logic

Port

Definition at line 41 of file CMX_generic_module_spy_mem_control_FSM.vhd.

clk in std_logic

Port

Definition at line 33 of file CMX_generic_module_spy_mem_control_FSM.vhd.

data_vme_in in std_logic_vector ( 15 downto 0 )

Port

Definition at line 39 of file CMX_generic_module_spy_mem_control_FSM.vhd.

data_vme_out out std_logic_vector ( 15 downto 0 )

Port

Definition at line 40 of file CMX_generic_module_spy_mem_control_FSM.vhd.

dina out std_logic_vector

Port

Definition at line 63 of file CMX_generic_module_spy_mem_control_FSM.vhd.

douta in std_logic_vector

Port

Definition at line 64 of file CMX_generic_module_spy_mem_control_FSM.vhd.

ds in std_logic

Port

Definition at line 37 of file CMX_generic_module_spy_mem_control_FSM.vhd.

ena out std_logic

Port

Definition at line 56 of file CMX_generic_module_spy_mem_control_FSM.vhd.

IEEE

Library

Definition at line 11 of file CMX_generic_module_spy_mem_control_FSM.vhd.

IEEE.MATH_REAL.all

Package

Definition at line 14 of file CMX_generic_module_spy_mem_control_FSM.vhd.

IEEE.NUMERIC_STD.all

Package

Definition at line 13 of file CMX_generic_module_spy_mem_control_FSM.vhd.

IEEE.STD_LOGIC_1164.all

Package

Definition at line 12 of file CMX_generic_module_spy_mem_control_FSM.vhd.

mem_select_address out std_logic_vector ( addr_port_width ( num_external_RAMS ) - 1 downto 0 )

Port

Definition at line 60 of file CMX_generic_module_spy_mem_control_FSM.vhd.

mode_control out std_logic_vector ( 3 downto 0 )

Port

Definition at line 43 of file CMX_generic_module_spy_mem_control_FSM.vhd.

ncs in std_logic

Port

Definition at line 35 of file CMX_generic_module_spy_mem_control_FSM.vhd.

num_external_RAMS positive := 1

Generic

Definition at line 28 of file CMX_generic_module_spy_mem_control_FSM.vhd.

port_b_master_inhibit out std_logic

Port

Definition at line 68 of file CMX_generic_module_spy_mem_control_FSM.vhd.

rd_nwr in std_logic

Port

Definition at line 36 of file CMX_generic_module_spy_mem_control_FSM.vhd.

UNISIM

Library

Definition at line 16 of file CMX_generic_module_spy_mem_control_FSM.vhd.

UNISIM.VComponents.all

Package

Definition at line 17 of file CMX_generic_module_spy_mem_control_FSM.vhd.

wea out std_logic

Port

Definition at line 57 of file CMX_generic_module_spy_mem_control_FSM.vhd.

work

Library

Definition at line 19 of file CMX_generic_module_spy_mem_control_FSM.vhd.

work.CMX_VME_defs.all

Package

Definition at line 21 of file CMX_generic_module_spy_mem_control_FSM.vhd.

work.CMXpackage.all

Package

Definition at line 20 of file CMX_generic_module_spy_mem_control_FSM.vhd.

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The documentation for this class was generated from the following file:

• Common/trunk/sources/CMX_generic_module_spy_mem_control_FSM.vhd