File List

Here is a list of all files with brief descriptions:

[detail level 12345]

Common
trunk
sources
adder_counter.vhd	This is the high-level counter module (rate metering) for all the flavors. This module uses mult_cnt component. The generic select the flavor and set the threshold number
and_all.vhd	Purely combinational circuit to compute and of all bits
BCID_counter.vhd	Loop over BCID's; reset to a pre-defined value
BUF_2X24_AT_80_TO_1X96_AT_40.vhd	De-serializer of DDR 160 Mbps data to 40 Mbps
cmm_board_select_rtl.vhd	VME infrastructure: selects (left or right) CMX
cmx_base_vme_bspt.vhd	VME infrastructure: detects thet this FPGA has been addressed and latches the port values
CMX_cable_clocked_80Mbps_input_module.vhd	Implements the input module for 80 Mbps source synchroneous
CMX_cable_clocked_80Mbps_output_module.vhd	Sends data on cable connector - together with 40 MHz clock on last
CMX_clock_manager.vhd	A wrapper for the global clock networks MMCMs and global buffers
CMX_crate_cable_output_module.vhd	Implements the output module for 80 Mbps source synchroneous transmission from the 'Crate' to the 'System' CMX and spy memories
CMX_CTP_output_module.vhd	Sends data at 40 Mbps on CTP cable connectors - together with 40 MHz clocks on the last pair of each connector
CMX_data_delay.vhd	This unit implements IODELAY for backplane inputs including the clocks
CMX_delay_generator.vhd	A wrapper for VME registers that set the delay values
CMX_generic_module_spy_mem_control_FSM.vhd	FSM for controlling access to spy memories via VME
CMX_input_module.vhd	This module captures data from the backplane
CMX_input_module_spy_mem_control_FSM.vhd	Obsolete: FSM for controlling access to input module spy memories via VME
CMX_Memory_spy_inhibit.vhd	A simple module that synchroneously stops writing to the spy memories
CMX_pipeline_module.vhd	The pipeline delay (CMX_pipeline_module) to delay the internal signal. The pipeline delay module uses the srl16 component. The output is delayed with respect to the input by n-ticks which are defined by the VME register
CMX_rate_counter_inhibit.vhd	Module to synchroneously stop and reset the rate counters
CMX_system_cable_input_module.vhd	Implements the input module for 80 Mbps source synchroneous transmission from the 'Crate' CMX and spy memories
CMX_version.vhd	A wrapper for VME registers that define the version numbers
CMX_VME_defs.vhd	VME address space for the CMXs
CMXpackage.vhd	This package defines all the types and constants common to all CMX types
CRC_CALC.vhd	Appends a 12 bit CRC code to the 128 bit trasnsmission that comes in 8 16 bit words
CRC_CHECK.vhd	Checks if the CRC of the transmission is 0
daq_glink.vhd	Formats and transfers data to the glink TX 40.00MHz domain
Delay.vhd	Delay input signal by number of ticks specified in the generic parameter
glink_encoder.vhd	This is the G-Link Encoder Module. The G-Link protocol was successfully implemented in Virtex-6. This protocol encodes 20 bits of user data
glink_interface.vhd	This is the G-Link interface, it uses glink encoder. The 24-bits of encoded data (clock 40 MHz) are "divided" into 3 x 8-bits of encoded data (clock 120 MHz)
input_latch_rtl.vhd	VME infreastructure
mini_fifo.vhd	Super-light weight fifo transferring data from one clock domain to next clocks must be exactly the same frequency but are of unknown phase relationship
mini_fifo_synchroniser.vhd	This modules provides synchronisers for the mini fifos that transfer the data into the GTX TX Clock domains
mult_cnt.vhd	Module (low-level) for counting the threshold acceptance rates. Two additional control signals are used: the reset and inhibit. The reset zeros the counters, while inhibit blocks the counters
or_all.vhd	Purely combinational circuit to compute or of all bits
PARITY_CALC.vhd	Purely combinational circuit to compute parity of numbitsinchan - 1 bits
parity_gen.vhd	The parity_gen module generates the parity of incoming data
Readout_FIFO.vhd	This module encapsulates two corgen FIFOs
rx_sync.vhd	Autogenerated file by the GTX wizard - synchronisation for the GTX's RX
SFP_TXRX.vhd	CMX common firmware module for transmitting data on the GTX driving the optical SFP (ROI and DAQ readout)
Stretch_10.vhd	Shift in the input signal 10 times and take or of all to stretch a short reset pulse
sys_monitor.vhd	Instantiates the system monitor and the VME interface for monitoring FPGA Temperature, voltage levels and currents
time_multiplex_8to1.vhd	Simple 8 to 1 time multiplexer used for transferring data at 320M words/s to the GTXs
Topo_Data_TX.vhd	CMX common firmware module for transmitting data to L1 Topo 24 channels 6.4 Gbps line rate each 8b/10b encoding. Instantiates and configures GTX transmitters
tx_sync.vhd	Auto-generated by xilinx GTX Wizard for synchronisation of the GTX's TX
vme_inreg_async_rtl.vhd	Read-Write only register without read/write event detection. This one has internal tri-states, suitable for partitioned design
vme_inreg_rtl.vhd	Read-Write only register with read event detection and write event detection. This one has internal tri-states, not suitable for partitioned design
vme_inreg_rtl_notri.vhd	Read-Write only register with read event detection and write event detection. This one has no internal tri-states, suitable for partitioned design
vme_inreg_rtl_notri_async.vhd	Read-Write register with no read/write event detection. This one has no internal tri-states, suitable for partitioned design
vme_local_switch.vhd	Local VME traffic switch
vme_main_hub.vhd	Main VME traffic switch; instatiates the tri-states; must be in the global partition
vme_outreg_rtl.vhd	Read only register with read event detection. This one has internal tri-states, not suitable for partitioned design
vme_outreg_rtl_notri.vhd	Read only register with read event detection. This one has no internal tri-states, suitable for partitioned design
vme_outreg_rtl_notri_async.vhd	Read only register with without read event detection. This one has no internal tri-states, suitable for partitioned design
CP
CP_common
trunk
sources
add3x4.vhd	The add4x3 module adds 4 3-bit numbers, return 3-bit result that saturates at 7
adder_top_vs_cp.vhd	The top level module (adder_top) for the multiplicty adder (CMX CP). Instantiates components that perform backplane interpretation to count objects over programmable thresholds; If instantiated in the system flavor also instantiates components that perform global summing and form the data to send to CTP
CMX_CP_Topo_Encoder.vhd	Purely combinational circuit. Takes data from the decoder and formats it for sending only 'real' logic is multiplexing in the send align signal
CMX_flavor_package.vhd	This package defines constants specific to CP CMX and common to crate and system varieties
CMX_top_Base_tb.vhd	The testbench module (CMX_top_Base_tb) which tests the CMX FW; The circuits generates the output and compares with the simulation. The error flag indicates the mismatch between the firmware and simulation
compExch.vhd	Comparison and exchange; This module sorts two TOBs according to Et (descending). This logic is used by the cp_decoder
cp_decoder.vhd	CMX data decoder based on sort, based on the jet decoder code. This logic implements a Bacher odd-even merge sort and takes upper 30 positions of the result to be loaded onto the Topo encoder and TX
daq_collector.vhd	Readout component. This module formats the data for the readout (glink stream) for the CP CMX. The parity error is calculated and enclosed to the data stream
main_crt_vs_cp.vhd	The crate module (main_crt) for the multiplicty adder (CMX CP). Interprets the backplane data to form local sums over threshold
main_sys_cp.vhd	The system module (main_sys) for the multiplicty adder (CMX CP). Receives the local and remote counts and calculates the global counts
parity_chk.vhd	The parity_chk module calculates the parity of incoming data and compare to received parity bit
parity_gen.vhd	The parity_gen module generates the parity of incoming data. NOTE: this logic is not obviously optimised for latency, but in practice it has a latency as low as anything that is
trig_sim.vhd
CP_crate
trunk
sources
CMX_cp_crate.ucf
CMX_local_package.vhd	Package definition for CP CMX crate specific configurations
CMX_top_Base.ucf
CMX_top_Base.vhd	Top level design for the CP CMX crate Base Function FPGA
CMX_top_Base_tb.vhd
CMX_top_Base_tb_topotx.vhd
CP_system
trunk
sources
CMX_cp_system.ucf
CMX_local_package.vhd	Package definition for CP CMX system specific configurations
CMX_top_Base.ucf
CMX_top_Base.vhd	Top level design for the CP CMX crate Base Function FPGA
CMX_top_Base_tb_topotx.vhd
Jet
Jet_common
trunk
sources
add2x2.vhd	The add2x2 module adds two 2-bit numbers, return 3-bit result that saturates at 3
add3x2.vhd	The add3x2 module adds two 3-bit numbers, return 3-bit result that saturates at 7
adder_top_vs.vhd	The top level module (adder_top) for the multiplicty adder (CMX JET). Instantiates components that perform backplane interpretation to count objects over programmable thresholds; If instantiated in the system flavor also instantiates components that perform global summing and form the data to send to CTP
CMX_flavor_package.vhd	This package defines constants specific to Jet CMX and common to crate and system varieties
CMX_Jet_Topo_Encoder.vhd
CMX_top_Base_tb.vhd	This the testbench which tests the JET CMX FW. The circuits generates the output and compares with the simulation. The error flag indicates the mismatch between the firmware and simulation
compExch.vhd	The compExch module. This module sorts two TOBs and its used by the jet_decoder
daq_collector.vhd	This module formats the data for the readout (glink stream). The parity error is calculated and enclosed to the data stream
jet_decoder.vhd	CMX data decoder based on sort (Bacher odd-even merge sort)
main_crt_vs.vhd	The crate module for the multiplicty adder (CMX JET). Interprets the backplane data to form local sums over threshold
main_sys.vhd	System module for the multiplicty adder (CMX JET). Receives the local and remote counts and calculates the global counts
parity_gen.vhd	The parity_gen module generates the parity of incoming data
trig_sim.vhd
Jet_crate
trunk
sources
CMX_jet_crate.ucf
CMX_local_package.vhd	Package definition for Jet CMX crate specific configurations
CMX_top_Base.ucf
CMX_top_Base.vhd	Top level design for the Jet crate Base Function FPGA
Jet_system
trunk
sources
CMX_jet_system.ucf
CMX_local_package.vhd	Package definition for Jet CMX system specific configurations
CMX_top_Base.ucf
CMX_top_Base.vhd	Top level design for the Jet system Base Function FPGA
CMX_top_Base_tb_topotx.vhd
RLOC_CompExch.ucf
mini_fifo_synchroniser.vhd
SumET
SumET_common
trunk
sources
CMX_flavor_package.vhd	This package defines constants specific to SumET CMX and common to crate and system varieties
CMX_SumEt.vhd	Encapsulates the main processing in the Sum ET: local and global energy summing
CMX_SumET_Topo_Encoder.vhd	Formats data to be sent to the TopoTX
crate_summing_module.vhd	This module performes EX EY ET sums of the local backplane data and the RTM cable output
daq_collector.vhd	Formats the data to be sent on DAQ and ROI links
system_summing_module.vhd	This module takes EX EY ET data received on the RTM cables and computed locally, then computes global sums and MET and sets XE TE and XS triggers
SumET_crate
trunk
sources
CMX_jet_crate.ucf
CMX_local_package.vhd	Package definition for Jet CMX crate specific configurations
CMX_top_Base.ucf
CMX_top_Base.vhd	Top level design for the SumET crate Base Function FPGA
SumET_system
trunk
sources
CMX_local_package.vhd	Package definition for SumET CMX system specific configurations
CMX_SumET_system.ucf
CMX_top_Base.ucf
CMX_top_Base.vhd	Top level design for the SumET system Base Function FPGA