![o](ftv2mnode.png) Common | |
![|](ftv2vertline.png) ![\](ftv2mlastnode.png) trunk | |
![|](ftv2vertline.png) ![](ftv2blank.png) ![\](ftv2mlastnode.png) sources | |
![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![o](ftv2node.png) adder_counter.vhd | This is the high-level counter module (rate metering) for all the flavors. This module uses mult_cnt component. The generic select the flavor and set the threshold number |
![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![o](ftv2node.png) and_all.vhd | Purely combinational circuit to compute and of all bits |
![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![o](ftv2node.png) BCID_counter.vhd | Loop over BCID's; reset to a pre-defined value |
![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![o](ftv2node.png) BUF_2X24_AT_80_TO_1X96_AT_40.vhd | De-serializer of DDR 160 Mbps data to 40 Mbps |
![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![o](ftv2node.png) cmm_board_select_rtl.vhd | VME infrastructure: selects (left or right) CMX |
![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![o](ftv2node.png) cmx_base_vme_bspt.vhd | VME infrastructure: detects thet this FPGA has been addressed and latches the port values |
![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![o](ftv2node.png) CMX_cable_clocked_80Mbps_input_module.vhd | Implements the input module for 80 Mbps source synchroneous |
![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![o](ftv2node.png) CMX_cable_clocked_80Mbps_output_module.vhd | Sends data on cable connector - together with 40 MHz clock on last |
![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![o](ftv2node.png) CMX_clock_manager.vhd | A wrapper for the global clock networks MMCMs and global buffers |
![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![o](ftv2node.png) CMX_crate_cable_output_module.vhd | Implements the output module for 80 Mbps source synchroneous transmission from the 'Crate' to the 'System' CMX and spy memories |
![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![o](ftv2node.png) CMX_CTP_output_module.vhd | Sends data at 40 Mbps on CTP cable connectors - together with 40 MHz clocks on the last pair of each connector |
![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![o](ftv2node.png) CMX_data_delay.vhd | This unit implements IODELAY for backplane inputs including the clocks |
![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![o](ftv2node.png) CMX_delay_generator.vhd | A wrapper for VME registers that set the delay values |
![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![o](ftv2node.png) CMX_generic_module_spy_mem_control_FSM.vhd | FSM for controlling access to spy memories via VME |
![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![o](ftv2node.png) CMX_input_module.vhd | This module captures data from the backplane |
![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![o](ftv2node.png) CMX_input_module_spy_mem_control_FSM.vhd | Obsolete: FSM for controlling access to input module spy memories via VME |
![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![o](ftv2node.png) CMX_Memory_spy_inhibit.vhd | A simple module that synchroneously stops writing to the spy memories |
![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![o](ftv2node.png) CMX_pipeline_module.vhd | The pipeline delay (CMX_pipeline_module) to delay the internal signal. The pipeline delay module uses the srl16 component. The output is delayed with respect to the input by n-ticks which are defined by the VME register |
![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![o](ftv2node.png) CMX_rate_counter_inhibit.vhd | Module to synchroneously stop and reset the rate counters |
![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![o](ftv2node.png) CMX_system_cable_input_module.vhd | Implements the input module for 80 Mbps source synchroneous transmission from the 'Crate' CMX and spy memories |
![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![o](ftv2node.png) CMX_version.vhd | A wrapper for VME registers that define the version numbers |
![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![o](ftv2node.png) CMX_VME_defs.vhd | VME address space for the CMXs |
![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![o](ftv2node.png) CMXpackage.vhd | This package defines all the types and constants common to all CMX types |
![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![o](ftv2node.png) CRC_CALC.vhd | Appends a 12 bit CRC code to the 128 bit trasnsmission that comes in 8 16 bit words |
![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![o](ftv2node.png) CRC_CHECK.vhd | Checks if the CRC of the transmission is 0 |
![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![o](ftv2node.png) daq_glink.vhd | Formats and transfers data to the glink TX 40.00MHz domain |
![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![o](ftv2node.png) Delay.vhd | Delay input signal by number of ticks specified in the generic parameter |
![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![o](ftv2node.png) glink_encoder.vhd | This is the G-Link Encoder Module. The G-Link protocol was successfully implemented in Virtex-6. This protocol encodes 20 bits of user data |
![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![o](ftv2node.png) glink_interface.vhd | This is the G-Link interface, it uses glink encoder. The 24-bits of encoded data (clock 40 MHz) are "divided" into 3 x 8-bits of encoded data (clock 120 MHz) |
![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![o](ftv2node.png) input_latch_rtl.vhd | VME infreastructure |
![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![o](ftv2node.png) mini_fifo.vhd | Super-light weight fifo transferring data from one clock domain to next clocks must be exactly the same frequency but are of unknown phase relationship |
![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![o](ftv2node.png) mini_fifo_synchroniser.vhd | This modules provides synchronisers for the mini fifos that transfer the data into the GTX TX Clock domains |
![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![o](ftv2node.png) mult_cnt.vhd | Module (low-level) for counting the threshold acceptance rates. Two additional control signals are used: the reset and inhibit. The reset zeros the counters, while inhibit blocks the counters |
![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![o](ftv2node.png) or_all.vhd | Purely combinational circuit to compute or of all bits |
![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![o](ftv2node.png) PARITY_CALC.vhd | Purely combinational circuit to compute parity of numbitsinchan - 1 bits |
![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![o](ftv2node.png) parity_gen.vhd | The parity_gen module generates the parity of incoming data |
![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![o](ftv2node.png) Readout_FIFO.vhd | This module encapsulates two corgen FIFOs |
![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![o](ftv2node.png) rx_sync.vhd | Autogenerated file by the GTX wizard - synchronisation for the GTX's RX |
![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![o](ftv2node.png) SFP_TXRX.vhd | CMX common firmware module for transmitting data on the GTX driving the optical SFP (ROI and DAQ readout) |
![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![o](ftv2node.png) Stretch_10.vhd | Shift in the input signal 10 times and take or of all to stretch a short reset pulse |
![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![o](ftv2node.png) sys_monitor.vhd | Instantiates the system monitor and the VME interface for monitoring FPGA Temperature, voltage levels and currents |
![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![o](ftv2node.png) time_multiplex_8to1.vhd | Simple 8 to 1 time multiplexer used for transferring data at 320M words/s to the GTXs |
![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![o](ftv2node.png) Topo_Data_TX.vhd | CMX common firmware module for transmitting data to L1 Topo 24 channels 6.4 Gbps line rate each 8b/10b encoding. Instantiates and configures GTX transmitters |
![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![o](ftv2node.png) tx_sync.vhd | Auto-generated by xilinx GTX Wizard for synchronisation of the GTX's TX |
![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![o](ftv2node.png) vme_inreg_async_rtl.vhd | Read-Write only register without read/write event detection. This one has internal tri-states, suitable for partitioned design |
![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![o](ftv2node.png) vme_inreg_rtl.vhd | Read-Write only register with read event detection and write event detection. This one has internal tri-states, not suitable for partitioned design |
![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![o](ftv2node.png) vme_inreg_rtl_notri.vhd | Read-Write only register with read event detection and write event detection. This one has no internal tri-states, suitable for partitioned design |
![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![o](ftv2node.png) vme_inreg_rtl_notri_async.vhd | Read-Write register with no read/write event detection. This one has no internal tri-states, suitable for partitioned design |
![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![o](ftv2node.png) vme_local_switch.vhd | Local VME traffic switch |
![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![o](ftv2node.png) vme_main_hub.vhd | Main VME traffic switch; instatiates the tri-states; must be in the global partition |
![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![o](ftv2node.png) vme_outreg_rtl.vhd | Read only register with read event detection. This one has internal tri-states, not suitable for partitioned design |
![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![o](ftv2node.png) vme_outreg_rtl_notri.vhd | Read only register with read event detection. This one has no internal tri-states, suitable for partitioned design |
![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![\](ftv2lastnode.png) vme_outreg_rtl_notri_async.vhd | Read only register with without read event detection. This one has no internal tri-states, suitable for partitioned design |
![o](ftv2mnode.png) CP | |
![|](ftv2vertline.png) ![o](ftv2mnode.png) CP_common | |
![|](ftv2vertline.png) ![|](ftv2vertline.png) ![\](ftv2mlastnode.png) trunk | |
![|](ftv2vertline.png) ![|](ftv2vertline.png) ![](ftv2blank.png) ![\](ftv2plastnode.png) sources | |
![|](ftv2vertline.png) ![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![o](ftv2node.png) add3x4.vhd | The add4x3 module adds 4 3-bit numbers, return 3-bit result that saturates at 7 |
![|](ftv2vertline.png) ![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![o](ftv2node.png) adder_top_vs_cp.vhd | The top level module (adder_top) for the multiplicty adder (CMX CP). Instantiates components that perform backplane interpretation to count objects over programmable thresholds; If instantiated in the system flavor also instantiates components that perform global summing and form the data to send to CTP |
![|](ftv2vertline.png) ![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![o](ftv2node.png) CMX_CP_Topo_Encoder.vhd | Purely combinational circuit. Takes data from the decoder and formats it for sending only 'real' logic is multiplexing in the send align signal |
![|](ftv2vertline.png) ![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![o](ftv2node.png) CMX_flavor_package.vhd | This package defines constants specific to CP CMX and common to crate and system varieties |
![|](ftv2vertline.png) ![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![o](ftv2node.png) CMX_top_Base_tb.vhd | The testbench module (CMX_top_Base_tb) which tests the CMX FW; The circuits generates the output and compares with the simulation. The error flag indicates the mismatch between the firmware and simulation |
![|](ftv2vertline.png) ![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![o](ftv2node.png) compExch.vhd | Comparison and exchange; This module sorts two TOBs according to Et (descending). This logic is used by the cp_decoder |
![|](ftv2vertline.png) ![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![o](ftv2node.png) cp_decoder.vhd | CMX data decoder based on sort, based on the jet decoder code. This logic implements a Bacher odd-even merge sort and takes upper 30 positions of the result to be loaded onto the Topo encoder and TX |
![|](ftv2vertline.png) ![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![o](ftv2node.png) daq_collector.vhd | Readout component. This module formats the data for the readout (glink stream) for the CP CMX. The parity error is calculated and enclosed to the data stream |
![|](ftv2vertline.png) ![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![o](ftv2node.png) main_crt_vs_cp.vhd | The crate module (main_crt) for the multiplicty adder (CMX CP). Interprets the backplane data to form local sums over threshold |
![|](ftv2vertline.png) ![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![o](ftv2node.png) main_sys_cp.vhd | The system module (main_sys) for the multiplicty adder (CMX CP). Receives the local and remote counts and calculates the global counts |
![|](ftv2vertline.png) ![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![o](ftv2node.png) parity_chk.vhd | The parity_chk module calculates the parity of incoming data and compare to received parity bit |
![|](ftv2vertline.png) ![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![o](ftv2node.png) parity_gen.vhd | The parity_gen module generates the parity of incoming data. NOTE: this logic is not obviously optimised for latency, but in practice it has a latency as low as anything that is |
![|](ftv2vertline.png) ![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![\](ftv2lastnode.png) trig_sim.vhd | |
![|](ftv2vertline.png) ![o](ftv2mnode.png) CP_crate | |
![|](ftv2vertline.png) ![|](ftv2vertline.png) ![\](ftv2mlastnode.png) trunk | |
![|](ftv2vertline.png) ![|](ftv2vertline.png) ![](ftv2blank.png) ![\](ftv2plastnode.png) sources | |
![|](ftv2vertline.png) ![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![o](ftv2node.png) CMX_cp_crate.ucf | |
![|](ftv2vertline.png) ![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![o](ftv2node.png) CMX_local_package.vhd | Package definition for CP CMX crate specific configurations |
![|](ftv2vertline.png) ![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![o](ftv2node.png) CMX_top_Base.ucf | |
![|](ftv2vertline.png) ![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![o](ftv2node.png) CMX_top_Base.vhd | Top level design for the CP CMX crate Base Function FPGA |
![|](ftv2vertline.png) ![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![o](ftv2node.png) CMX_top_Base_tb.vhd | |
![|](ftv2vertline.png) ![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![\](ftv2lastnode.png) CMX_top_Base_tb_topotx.vhd | |
![|](ftv2vertline.png) ![\](ftv2mlastnode.png) CP_system | |
![|](ftv2vertline.png) ![](ftv2blank.png) ![\](ftv2mlastnode.png) trunk | |
![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![\](ftv2plastnode.png) sources | |
![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![](ftv2blank.png) ![o](ftv2node.png) CMX_cp_system.ucf | |
![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![](ftv2blank.png) ![o](ftv2node.png) CMX_local_package.vhd | Package definition for CP CMX system specific configurations |
![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![](ftv2blank.png) ![o](ftv2node.png) CMX_top_Base.ucf | |
![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![](ftv2blank.png) ![o](ftv2node.png) CMX_top_Base.vhd | Top level design for the CP CMX crate Base Function FPGA |
![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![](ftv2blank.png) ![\](ftv2lastnode.png) CMX_top_Base_tb_topotx.vhd | |
![o](ftv2mnode.png) Jet | |
![|](ftv2vertline.png) ![o](ftv2mnode.png) Jet_common | |
![|](ftv2vertline.png) ![|](ftv2vertline.png) ![\](ftv2mlastnode.png) trunk | |
![|](ftv2vertline.png) ![|](ftv2vertline.png) ![](ftv2blank.png) ![\](ftv2plastnode.png) sources | |
![|](ftv2vertline.png) ![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![o](ftv2node.png) add2x2.vhd | The add2x2 module adds two 2-bit numbers, return 3-bit result that saturates at 3 |
![|](ftv2vertline.png) ![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![o](ftv2node.png) add3x2.vhd | The add3x2 module adds two 3-bit numbers, return 3-bit result that saturates at 7 |
![|](ftv2vertline.png) ![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![o](ftv2node.png) adder_top_vs.vhd | The top level module (adder_top) for the multiplicty adder (CMX JET). Instantiates components that perform backplane interpretation to count objects over programmable thresholds; If instantiated in the system flavor also instantiates components that perform global summing and form the data to send to CTP |
![|](ftv2vertline.png) ![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![o](ftv2node.png) CMX_flavor_package.vhd | This package defines constants specific to Jet CMX and common to crate and system varieties |
![|](ftv2vertline.png) ![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![o](ftv2node.png) CMX_Jet_Topo_Encoder.vhd | |
![|](ftv2vertline.png) ![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![o](ftv2node.png) CMX_top_Base_tb.vhd | This the testbench which tests the JET CMX FW. The circuits generates the output and compares with the simulation. The error flag indicates the mismatch between the firmware and simulation |
![|](ftv2vertline.png) ![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![o](ftv2node.png) compExch.vhd | The compExch module. This module sorts two TOBs and its used by the jet_decoder |
![|](ftv2vertline.png) ![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![o](ftv2node.png) daq_collector.vhd | This module formats the data for the readout (glink stream). The parity error is calculated and enclosed to the data stream |
![|](ftv2vertline.png) ![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![o](ftv2node.png) jet_decoder.vhd | CMX data decoder based on sort (Bacher odd-even merge sort) |
![|](ftv2vertline.png) ![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![o](ftv2node.png) main_crt_vs.vhd | The crate module for the multiplicty adder (CMX JET). Interprets the backplane data to form local sums over threshold |
![|](ftv2vertline.png) ![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![o](ftv2node.png) main_sys.vhd | System module for the multiplicty adder (CMX JET). Receives the local and remote counts and calculates the global counts |
![|](ftv2vertline.png) ![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![o](ftv2node.png) parity_gen.vhd | The parity_gen module generates the parity of incoming data |
![|](ftv2vertline.png) ![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![\](ftv2lastnode.png) trig_sim.vhd | |
![|](ftv2vertline.png) ![o](ftv2mnode.png) Jet_crate | |
![|](ftv2vertline.png) ![|](ftv2vertline.png) ![\](ftv2mlastnode.png) trunk | |
![|](ftv2vertline.png) ![|](ftv2vertline.png) ![](ftv2blank.png) ![\](ftv2plastnode.png) sources | |
![|](ftv2vertline.png) ![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![o](ftv2node.png) CMX_jet_crate.ucf | |
![|](ftv2vertline.png) ![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![o](ftv2node.png) CMX_local_package.vhd | Package definition for Jet CMX crate specific configurations |
![|](ftv2vertline.png) ![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![o](ftv2node.png) CMX_top_Base.ucf | |
![|](ftv2vertline.png) ![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![\](ftv2lastnode.png) CMX_top_Base.vhd | Top level design for the Jet crate Base Function FPGA |
![|](ftv2vertline.png) ![\](ftv2mlastnode.png) Jet_system | |
![|](ftv2vertline.png) ![](ftv2blank.png) ![\](ftv2mlastnode.png) trunk | |
![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![o](ftv2pnode.png) sources | |
![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![|](ftv2vertline.png) ![o](ftv2node.png) CMX_jet_system.ucf | |
![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![|](ftv2vertline.png) ![o](ftv2node.png) CMX_local_package.vhd | Package definition for Jet CMX system specific configurations |
![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![|](ftv2vertline.png) ![o](ftv2node.png) CMX_top_Base.ucf | |
![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![|](ftv2vertline.png) ![o](ftv2node.png) CMX_top_Base.vhd | Top level design for the Jet system Base Function FPGA |
![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![|](ftv2vertline.png) ![o](ftv2node.png) CMX_top_Base_tb_topotx.vhd | |
![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![|](ftv2vertline.png) ![\](ftv2lastnode.png) RLOC_CompExch.ucf | |
![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![\](ftv2lastnode.png) mini_fifo_synchroniser.vhd | |
![\](ftv2mlastnode.png) SumET | |
![](ftv2blank.png) ![o](ftv2mnode.png) SumET_common | |
![](ftv2blank.png) ![|](ftv2vertline.png) ![\](ftv2mlastnode.png) trunk | |
![](ftv2blank.png) ![|](ftv2vertline.png) ![](ftv2blank.png) ![\](ftv2plastnode.png) sources | |
![](ftv2blank.png) ![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![o](ftv2node.png) CMX_flavor_package.vhd | This package defines constants specific to SumET CMX and common to crate and system varieties |
![](ftv2blank.png) ![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![o](ftv2node.png) CMX_SumEt.vhd | Encapsulates the main processing in the Sum ET: local and global energy summing |
![](ftv2blank.png) ![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![o](ftv2node.png) CMX_SumET_Topo_Encoder.vhd | Formats data to be sent to the TopoTX |
![](ftv2blank.png) ![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![o](ftv2node.png) crate_summing_module.vhd | This module performes EX EY ET sums of the local backplane data and the RTM cable output |
![](ftv2blank.png) ![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![o](ftv2node.png) daq_collector.vhd | Formats the data to be sent on DAQ and ROI links |
![](ftv2blank.png) ![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![\](ftv2lastnode.png) system_summing_module.vhd | This module takes EX EY ET data received on the RTM cables and computed locally, then computes global sums and MET and sets XE TE and XS triggers |
![](ftv2blank.png) ![o](ftv2mnode.png) SumET_crate | |
![](ftv2blank.png) ![|](ftv2vertline.png) ![\](ftv2mlastnode.png) trunk | |
![](ftv2blank.png) ![|](ftv2vertline.png) ![](ftv2blank.png) ![\](ftv2plastnode.png) sources | |
![](ftv2blank.png) ![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![o](ftv2node.png) CMX_jet_crate.ucf | |
![](ftv2blank.png) ![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![o](ftv2node.png) CMX_local_package.vhd | Package definition for Jet CMX crate specific configurations |
![](ftv2blank.png) ![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![o](ftv2node.png) CMX_top_Base.ucf | |
![](ftv2blank.png) ![|](ftv2vertline.png) ![](ftv2blank.png) ![](ftv2blank.png) ![\](ftv2lastnode.png) CMX_top_Base.vhd | Top level design for the SumET crate Base Function FPGA |
![](ftv2blank.png) ![\](ftv2mlastnode.png) SumET_system | |
![](ftv2blank.png) ![](ftv2blank.png) ![\](ftv2mlastnode.png) trunk | |
![](ftv2blank.png) ![](ftv2blank.png) ![](ftv2blank.png) ![\](ftv2plastnode.png) sources | |
![](ftv2blank.png) ![](ftv2blank.png) ![](ftv2blank.png) ![](ftv2blank.png) ![o](ftv2node.png) CMX_local_package.vhd | Package definition for SumET CMX system specific configurations |
![](ftv2blank.png) ![](ftv2blank.png) ![](ftv2blank.png) ![](ftv2blank.png) ![o](ftv2node.png) CMX_SumET_system.ucf | |
![](ftv2blank.png) ![](ftv2blank.png) ![](ftv2blank.png) ![](ftv2blank.png) ![o](ftv2node.png) CMX_top_Base.ucf | |
![](ftv2blank.png) ![](ftv2blank.png) ![](ftv2blank.png) ![](ftv2blank.png) ![\](ftv2lastnode.png) CMX_top_Base.vhd | Top level design for the SumET system Base Function FPGA |