vme_outreg_rtl.vhd

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LIBRARY ieee ;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;


use work.CMXpackage.all;
use work.CMX_VME_defs.all;

entity vme_outreg is
  generic( 
    ia_vme : integer := 0;
    width  : integer := 16
    );
  port(
    clk : in std_logic; 
    
    ncs      : in     std_logic;
    rd_nwr   : in     std_logic;
    ds       : in     std_logic;

    addr_vme : in     std_logic_vector (15 downto 0);
    data_vme : out    std_logic_vector (15 downto 0);
    
    data_to_vme  : in     std_logic_vector (width-1 downto 0);
    read_detect : out std_logic
    );

-- Declarations

end vme_outreg ;
--------------------------------------------------------------------------------
ARCHITECTURE rtl OF vme_outreg IS
--------------------------------------------------------------------------------
-- VME register, all bits are inputs to board (q).
-- Variable width q, max 16.
--

  signal ren: std_logic; -- vme read enable
  signal ren_r,ren_rr,ren_rrr,ren_rrrr,ren_rrrrr,ren_rrrrrr: std_logic; --above
                                                                        --registered to
                                                                        --sys clk

  signal ds_r,ds_rr,ds_rrr,ds_rrrr,ds_rrrrr,ds_rrrrrr,ds_rrrrrrr,ds_rrrrrrrr : std_logic; -- previous
                                                                   -- registered
                                                                   -- value of strobe

  signal read_detect_sig : std_logic;
  signal read_detect_delay_line : std_logic_vector(VME_read_det_delay-1 downto 0);


  
--------------------------------------------------------------------------------
BEGIN


  ren <= vme_ren (ia_vme, addr_vme, ncs, rd_nwr);


  vme_r_proc: process (ren, data_to_vme)
    -- read access
  begin
    data_vme <= "ZZZZZZZZZZZZZZZZ";
    if (ren = '1') then
      data_vme <= (others=>'0');
      data_vme(width-1 downto 0) <= data_to_vme;
    end if;    
  end process; 

  -- detect a read enable edge and generate a pulse on read_detect signal
  read_detect_proc: process (clk)
  begin  -- process read_detect_proc
    if rising_edge(clk) then  -- rising clock edge
      if ren_rrrrrr='1' and ren_rrrrr='1' and ren_rrrr='1' and ren_rrr='1' and ren_rr='1' and ren_r='1'
        and ds_rrrrrrrr='0' and ds_rrrrrrr='0'  and ds_rrrrrr='0' and ds_rrrrr='1' and ds_rrrr='1'  and ds_rrr='1'
      then
        read_detect_sig <= '1';
      else
        read_detect_sig <= '0';
      end if;
      ren_rrrrrr<=ren_rrrrr;
      ren_rrrrr<=ren_rrrr;
      ren_rrrr<=ren_rrr;
      ren_rrr<=ren_rr;
      ren_rr<=ren_r;
      ren_r<=ren;

      ds_rrrrrrrr<=ds_rrrrrrr;
      ds_rrrrrrr<=ds_rrrrrr;
      ds_rrrrrr<=ds_rrrrr;
      ds_rrrrr<=ds_rrrr;
      ds_rrrr<=ds_rrr;
      ds_rrr<=ds_rr;
      ds_rr<=ds_r;
      ds_r<=ds;
      
    end if;
  end process read_detect_proc;

  
  read_detect_delay_line(0)<=read_detect_sig;
  gen_read_detect_delay: for i_del in 1 to VME_read_det_delay-1 generate
    process(clk)
    begin
      if rising_edge(clk) then
        read_detect_delay_line(i_del)<=read_detect_delay_line(i_del-1);
      end if;
    end process;
  end generate gen_read_detect_delay;
  
  read_detect<=read_detect_delay_line(VME_read_det_delay-1);
  
END rtl;