sources Directory Reference

Files
file	adder_counter.vhd [code]
	This is the high-level counter module (rate metering) for all the flavors. This module uses mult_cnt component. The generic select the flavor and set the threshold number.
file	and_all.vhd [code]
	Purely combinational circuit to compute and of all bits.
file	BCID_counter.vhd [code]
	loop over BCID's; reset to a pre-defined value
file	BUF_2X24_AT_80_TO_1X96_AT_40.vhd [code]
	de-serializer of DDR 160 Mbps data to 40 Mbps
file	cmm_board_select_rtl.vhd [code]
	VME infrastructure: selects (left or right) CMX.
file	cmx_base_vme_bspt.vhd [code]
	VME infrastructure: detects thet this FPGA has been addressed and latches the port values.
file	CMX_cable_clocked_80Mbps_input_module.vhd [code]
	Implements the input module for 80 Mbps source synchroneous.
file	CMX_cable_clocked_80Mbps_output_module.vhd [code]
	sends data on cable connector - together with 40 MHz clock on last
file	CMX_clock_manager.vhd [code]
	A wrapper for the global clock networks MMCMs and global buffers.
file	CMX_crate_cable_output_module.vhd [code]
	Implements the output module for 80 Mbps source synchroneous transmission from the 'Crate' to the 'System' CMX and spy memories.
file	CMX_CTP_output_module.vhd [code]
	Sends data at 40 Mbps on CTP cable connectors - together with 40 MHz clocks on the last pair of each connector.
file	CMX_data_delay.vhd [code]
	This unit implements IODELAY for backplane inputs including the clocks.
file	CMX_delay_generator.vhd [code]
	A wrapper for VME registers that set the delay values.
file	CMX_generic_module_spy_mem_control_FSM.vhd [code]
	FSM for controlling access to spy memories via VME.
file	CMX_input_module.vhd [code]
	This module captures data from the backplane.
file	CMX_input_module_spy_mem_control_FSM.vhd [code]
	obsolete: FSM for controlling access to input module spy memories via VME
file	CMX_Memory_spy_inhibit.vhd [code]
	A simple module that synchroneously stops writing to the spy memories.
file	CMX_pipeline_module.vhd [code]
	The pipeline delay (CMX_pipeline_module) to delay the internal signal. The pipeline delay module uses the srl16 component. The output is delayed with respect to the input by n-ticks which are defined by the VME register.
file	CMX_rate_counter_inhibit.vhd [code]
	module to synchroneously stop and reset the rate counters
file	CMX_system_cable_input_module.vhd [code]
	Implements the input module for 80 Mbps source synchroneous transmission from the 'Crate' CMX and spy memories.
file	CMX_version.vhd [code]
	A wrapper for VME registers that define the version numbers.
file	CMX_VME_defs.vhd [code]
	provides VME address space for the CMXs
file	CMXpackage.vhd [code]
	This package defines all the types and constants common to all CMX types.
file	CRC_CALC.vhd [code]
	appends a 12 bit CRC code to the 128 bit trasnsmission that comes in 8 16 bit words
file	CRC_CHECK.vhd [code]
	checks if the CRC of the transmission is 0
file	daq_glink.vhd [code]
	Formats and transfers data to the glink TX 40.00MHz domain.
file	Delay.vhd [code]
	delay input signal by number of ticks specified in the generic parameter.
file	glink_encoder.vhd [code]
	This is the G-Link Encoder Module. The G-Link protocol was successfully implemented in Virtex-6. This protocol encodes 20 bits of user data.
file	glink_interface.vhd [code]
	This is the G-Link interface, it uses glink encoder. The 24-bits of encoded data (clock 40 MHz) are "divided" into 3 x 8-bits of encoded data (clock 120 MHz).
file	input_latch_rtl.vhd [code]
	VME infreastructure.
file	mini_fifo.vhd [code]
	Super-light weight fifo transferring data from one clock domain to next clocks must be exactly the same frequency but are of unknown phase relationship.
file	mini_fifo_synchroniser.vhd [code]
	this modules provides synchronisers for the mini fifos that transfer the data into the GTX TX Clock domains
file	mult_cnt.vhd [code]
	Module (low-level) for counting the threshold acceptance rates. Two additional control signals are used: the reset and inhibit. The reset zeros the counters, while inhibit blocks the counters.
file	or_all.vhd [code]
	Purely combinational circuit to compute or of all bits.
file	PARITY_CALC.vhd [code]
	Purely combinational circuit to compute parity of numbitsinchan - 1 bits.
file	parity_gen.vhd [code]
	The parity_gen module generates the parity of incoming data.
file	Readout_FIFO.vhd [code]
	This module encapsulates two corgen FIFOs.
file	rx_sync.vhd [code]
	autogenerated file by the GTX wizard - synchronisation for the GTX's RX
file	SFP_TXRX.vhd [code]
	CMX common firmware module for transmitting data on the GTX driving the optical SFP (ROI and DAQ readout)
file	Stretch_10.vhd [code]
	shift in the input signal 10 times and take or of all to stretch a short reset pulse
file	sys_monitor.vhd [code]
	Instantiates the system monitor and the VME interface for monitoring FPGA Temperature, voltage levels and currents.
file	time_multiplex_8to1.vhd [code]
	Simple 8 to 1 time multiplexer used for transferring data at 320M words/s to the GTXs.
file	Topo_Data_TX.vhd [code]
	CMX common firmware module for transmitting data to L1 Topo 24 channels 6.4 Gbps line rate each 8b/10b encoding. Instantiates and configures GTX transmitters.
file	tx_sync.vhd [code]
	auto-generated by xilinx GTX Wizard for synchronisation of the GTX's TX
file	vme_inreg_async_rtl.vhd [code]
	Read-Write only register without read/write event detection. This one has internal tri-states, suitable for partitioned design.
file	vme_inreg_rtl.vhd [code]
	Read-Write only register with read event detection and write event detection. This one has internal tri-states, not suitable for partitioned design.
file	vme_inreg_rtl_notri.vhd [code]
	Read-Write only register with read event detection and write event detection. This one has no internal tri-states, suitable for partitioned design.
file	vme_inreg_rtl_notri_async.vhd [code]
	Read-Write register with no read/write event detection. This one has no internal tri-states, suitable for partitioned design.
file	vme_local_switch.vhd [code]
	local VME traffic switch
file	vme_main_hub.vhd [code]
	main VME traffic switch; instatiates the tri-states; must be in the global partition
file	vme_outreg_rtl.vhd [code]
	Read only register with read event detection. This one has internal tri-states, not suitable for partitioned design.
file	vme_outreg_rtl_notri.vhd [code]
	Read only register with read event detection. This one has no internal tri-states, suitable for partitioned design.
file	vme_outreg_rtl_notri_async.vhd [code]
	Read only register with without read event detection. This one has no internal tri-states, suitable for partitioned design.