CMX_cable_clocked_80Mbps_output_module.vhd

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

library UNISIM;
use UNISIM.VComponents.all;

library work;
use work.CMXpackage.all;


entity CMX_cable_clocked_80Mbps_output_module is
  generic (
    numbits_in_cable_connector : integer);
  port (
    data : in std_logic_vector( (numbits_in_cable_connector*2)-1 downto 0);
    ddr_data_out              : out std_logic_vector(numbits_in_cable_connector downto 0); --
    --includes clock
    buf_clk40          : in std_logic;       -- global 40 MHz clock
    buf_clk40_center   : in std_logic;       -- global 40 MHz clock pushed by 90^o
    buf_clk200         : in std_logic;       -- global 200 MHz clock for iodelay calibration
    pll_locked         : in std_logic;       -- is the main MMCM locked?
        
    del_array: in cable_del_array_type(numbits_in_cable_connector downto 0);
    upload_delays: in std_logic
    );
  
end CMX_cable_clocked_80Mbps_output_module;

architecture Behavioral of CMX_cable_clocked_80Mbps_output_module is


  signal PDATA : std_logic_vector(numbits_in_cable_connector-1 downto 0);  --DDR data
  signal NDATA : std_logic_vector(numbits_in_cable_connector-1 downto 0);
  
  signal ddr_data_out_nondel : std_logic_vector(numbits_in_cable_connector downto 0);
  

  signal i_pll_locked: std_logic;


  
  

  --component CMX_output_data_delay
  --  port (
  --    data_in        : in  mat_var(numactchan-1 downto 0);
  --    data_out       : out mat_var(numactchan-1 downto 0);
  --    REF_CLK_200    : in  std_logic;
  --    REF_CLK_READY  : in  std_logic;
  --    CLK_40         : in  std_logic;
  --    del_register   : in  del_register_type;
  --    upload_delays  : in  std_logic;
  --    IDELAYCTRL_RDY : out std_logic_vector(num_IDELAYCTRL-1 downto 0));
  --end component;

  
begin

  

  i_pll_locked<= not pll_locked;
  
  PDATA<=data(numbits_in_cable_connector-1 downto 0);
  NDATA<=data(numbits_in_cable_connector*2 - 1 downto numbits_in_cable_connector);
  
  --now connect to ODDR
  bitgen: for bitnum in 0 to (numbits_in_cable_connector-1) generate
    
    ODDR_inst : ODDR
      generic map(
        DDR_CLK_EDGE  => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE" 
        INIT  => '0',   -- Initial value for Q port ('1' or '0')
        SRTYPE  => "SYNC") -- Reset Type ("ASYNC" or "SYNC")
      port map (
        Q  => ddr_data_out_nondel(bitnum),   -- 1-bit DDR output
        C  => buf_clk40,    -- 1-bit clock input
        CE  => '1',  -- 1-bit clock enable input
        D1  => PDATA(bitnum),  -- 1-bit data input (positive edge)
        D2  => NDATA(bitnum),  -- 1-bit data input (negative edge)
        R  => i_pll_locked,    -- 1-bit reset input
        S  => '0'     -- 1-bit set input
        );
    
  end generate bitgen;

  --generate forwarded clock
  ODDR_inst : ODDR
    generic map(
      DDR_CLK_EDGE  => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE" 
      INIT  => '0',   -- Initial value for Q port ('1' or '0')
      SRTYPE  => "SYNC") -- Reset Type ("ASYNC" or "SYNC")
    port map (
      Q  => ddr_data_out_nondel(numbits_in_cable_connector),   -- 1-bit DDR output
      C  => buf_clk40_center ,    -- 1-bit clock input
      CE  => '1',  -- 1-bit clock enable input
      D1  => '1',  -- 1-bit data input (positive edge)
      D2  => '0',  -- 1-bit data input (negative edge)
      R  => i_pll_locked,    -- 1-bit reset input
      S  => '0'     -- 1-bit set input
      );
    
   ddr_data_out<=ddr_data_out_nondel;
  
  --for now no delay circuits

  
  
  ----the output delay module
  --CMX_output_data_delay_inst: CMX_output_data_delay
  --  port map (
  --    data_in        => P_out_nondel,
  --    data_out       => P_out,
  --    REF_CLK_200    => buf_clk200,
  --    REF_CLK_READY  => pll_locked,
  --    CLK_40         => buf_clk40,
  --    del_register   => del_register,
  --    upload_delays  => upload_delays,
  --    IDELAYCTRL_RDY => open);
  --
  --counter_enable_out<=counter_enable;

  
  
end Behavioral;