CMX_cable_clocked_80Mbps_input_module.vhd

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----------------------------------------------------------------------------------
--transmission over the RTM cables 
----------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

library UNISIM;
use UNISIM.VComponents.all;

library work;
use work.CMXpackage.all;


entity CMX_cable_clocked_80Mbps_input_module is
  generic (
    numbits_in_cable_connector : integer);
  port (
    data : out std_logic_vector( (numbits_in_cable_connector*2)-1 downto 0);
    parity_error : out std_logic;
    forwarded_clock : out std_logic;
    ddr_data_in : in std_logic_vector(numbits_in_cable_connector downto 0); 
    buf_clk40   : in std_logic;       -- global 40 MHz clock
    buf_clk200  : in std_logic;       -- global 200 MHz clock for iodelay calibration
    pll_locked  : in std_logic;       -- is the main MMCM locked?
    del_array   : in cable_del_array_type(numbits_in_cable_connector downto 0);
    upload_delays: in std_logic
    );
  
end CMX_cable_clocked_80Mbps_input_module;


architecture Behavioral of CMX_cable_clocked_80Mbps_input_module is



  signal delayed_ddr_data_in : std_logic_vector(numbits_in_cable_connector-1 downto 0); -- after putting the
                                                                                   -- data through the
                                                                                   -- delay module

  signal delayed_cable_clock : std_logic;
  signal delayed_cable_clock_buffered: std_logic;

  signal PDATA, NDATA: std_logic_vector(numbits_in_cable_connector - 1 downto 0);

  signal i_pll_locked: std_logic;

  signal parity_P : std_logic;
  signal parity_N : std_logic;
  signal parity_P_tmp : std_logic_vector(numbits_in_cable_connector - 1  downto 0);
  signal parity_N_tmp : std_logic_vector(numbits_in_cable_connector - 1  downto 0);  
  

  --component CMX_RTM_data_delay
  --  generic (
  --    inst_IDELAYCTRL: std_logic :='1');
  --  port (
  --    RTM_data         : in  std_logic_vector(numbitsinchan_LVDS_RTM downto 0);
  --    REF_CLK_200      : in  std_logic;
  --    REF_CLK_READY    : in  std_logic;
  --    CLK_40           : in  std_logic;
  --    del_register     : in  del_register_rtm_type;
  --    upload_delays    : in  std_logic;
  --    IDELAYCTRL_RDY   : out std_logic;
  --    delayed_RTM_data : out std_logic_vector(numbitsinchan_LVDS_RTM downto 0));
  --end component;


begin

  
  --the data straight from the RTM module are passed through the IDELAY
  -- CMX_RTM_data_delay_i: CMX_RTM_data_delay
  --   generic map (
  --     inst_IDELAYCTRL => inst_IDELAYCTRL)
  --   port map (
  --     RTM_data         => RTM_data,
  --     REF_CLK_200      => buf_clk200,
  --     REF_CLK_READY    => pll_locked,
  --     CLK_40           => buf_clk40,
  --     del_register     => del_register_rtm,
  --     upload_delays    => upload_delays,
  --     IDELAYCTRL_RDY   => open,
  --     delayed_RTM_data(numbitsinchan_LVDS_RTM-1 downto 0) => delayed_RTM_data,
  --     delayed_RTM_data(numbitsinchan_LVDS_RTM) => delayed_RTM_clock);
  --
  delayed_ddr_data_in<=ddr_data_in(numbits_in_cable_connector-1 downto 0);
  delayed_cable_clock<=ddr_data_in(numbits_in_cable_connector);
  
  BUFR_inst : BUFR
    generic map (
      BUFR_DIVIDE  => "BYPASS", -- Values: "BYPASS", "1", "2", "3", "4", "5", "6", "7", "8" 
      SIM_DEVICE  => "VIRTEX6"  -- Must be set to "VIRTEX6" 
      )
    port map (
      O  => delayed_cable_clock_buffered,
      CE  => '1',
      CLR  => '0',
      I  => delayed_cable_clock
      );

  --- BUFG_inst: BUFG
  ---   port map (
  ---     O => delayed_cable_clock_buffered,
  ---     I => delayed_cable_clock);
  
  i_pll_locked <= not pll_locked;
  
  bitgen: for bitnum in 0 to numbits_in_cable_connector - 1 generate
    IDDR_inst : IDDR  
      generic map (
        DDR_CLK_EDGE  => "OPPOSITE_EDGE", --"SAME_EDGE_PIPELINED", -- "OPPOSITE_EDGE", "SAME_EDGE" 
        -- or "SAME_EDGE_PIPELINED" 
        INIT_Q1  => '0', -- Initial value of Q1: '0' or '1'
        INIT_Q2  => '0', -- Initial value of Q2: '0' or '1'
        SRTYPE  => "SYNC") -- Set/Reset type: "SYNC" or "ASYNC"
      port map (
        Q1  => PDATA(bitnum), -- 1-bit output for positive edge of clock 
        Q2  => NDATA(bitnum), -- 1-bit output for negative edge of clock
        C  => delayed_cable_clock_buffered,   -- 1-bit clock input
        CE  => '1', -- 1-bit clock enable input
        D  => delayed_ddr_data_in(bitnum),   -- 1-bit DDR data input
        R  => i_pll_locked,   -- 1-bit reset
        S  => '0'    -- 1-bit set
        );        
  end generate bitgen;

  process(delayed_cable_clock_buffered)
  begin
    if rising_edge(delayed_cable_clock_buffered) then
      data( (numbits_in_cable_connector*2)-1 downto numbits_in_cable_connector) <= NDATA;
      data( numbits_in_cable_connector-1 downto 0) <= PDATA;
      parity_error<=parity_P or parity_N;
    end if;
  end process;

  parity_P_tmp(0) <=PDATA(0) xor '1';
  xor_gen_P: for bitnum in 1 to (numbits_in_cable_connector-1) generate
    parity_P_tmp(bitnum) <= PDATA(bitnum) xor parity_P_tmp(bitnum-1);
  end generate xor_gen_P;
  parity_P<=parity_P_tmp(numbits_in_cable_connector-1);

  parity_N_tmp(0) <=NDATA(0) xor '1';
  xor_gen_N: for bitnum in 1 to (numbits_in_cable_connector-1) generate
    parity_N_tmp(bitnum) <= NDATA(bitnum) xor parity_N_tmp(bitnum-1);
  end generate xor_gen_N;
  parity_N<=parity_N_tmp(numbits_in_cable_connector-1);


  forwarded_clock<=delayed_cable_clock_buffered;
  
end Behavioral;