cmx_base_vme_bspt.vhd

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-- VHDL Entity cmm_vme_cpld.vme_interface.symbol
--
-- Created:
--          by - ipb28.UNKNOWN (TE2MALDIVES)
--          at - 15:02:25 29/08/2008
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
--
-- from 11.01.2014 modified by YE for CMX ("ye_rw80" and "ye_rw82" removed)
-- from 15.01.2014 modified by YE for CMX_BASE FPGA (name changed from vme_interface to CMX_BASE_VME_INTERFACE)

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
--use work.cmx_pkg.all; -- modified CMM packages vme_cmm and cmm_array_types(Ian)


ENTITY CMX_BASE_VME_BSPT IS
   PORT(                                                       
      clk40       : IN     std_logic;                       -- 40MHz Clk     
      geoadd_0    : IN     std_logic;                       -- GeoAddr0      
      n_ds0_int   : IN     std_logic;                       -- DS strobe     
      n_write     : IN     std_logic;                       -- VME Write     
      vme_address : IN     std_logic_vector (23 DOWNTO 1);  -- Address bus   
      board_ds    : OUT    std_logic;                       -- Board ds    
      brdsel_n    : OUT    std_logic                        -- Board select  
        );
END CMX_BASE_VME_BSPT ;


ARCHITECTURE STR OF CMX_BASE_VME_BSPT IS

   -- Component Declarations
    
   COMPONENT input_latch
   PORT (
      n_ds0_int     : IN     std_logic;
      n_write       : IN     std_logic;
      vme_address   : IN     std_logic_vector (23 DOWNTO 1);
      address_ltchd : OUT    std_logic_vector (23 DOWNTO 1);
      n_write_ltchd : OUT    std_logic 
   );
   END COMPONENT;
    -- internal signals for input_latch
    SIGNAL address_ltchd      : std_logic_vector(23 DOWNTO 1);
    SIGNAL n_write_ltchd      : std_logic;
    
   COMPONENT CMM_Board_Select
   PORT (
      addressbus     : IN     std_logic_vector (23 DOWNTO 19);
      geoaddr_0      : IN     std_logic;
      board_select_n : OUT    std_logic
   );
   END COMPONENT;
    -- internal signals for CMM_Board_Select
    SIGNAL board_select_n     : std_logic;
    
BEGIN
    
   -- vme_interface output signals
   board_ds      <= board_select_n nor n_ds0_int;
   brdsel_n      <= board_select_n;

   -- Instance port mappings
    
   VMEIF_input_latch : input_latch
      PORT MAP (
         n_ds0_int     => n_ds0_int,
         n_write       => n_write,
         vme_address   => vme_address,
         address_ltchd => address_ltchd,
         n_write_ltchd => n_write_ltchd
      );

   VMEIF_CMM_Board_Select : CMM_Board_Select
      PORT MAP (
         addressbus      => address_ltchd(23 DOWNTO 19),
         geoaddr_0       => geoadd_0,
         board_select_n  => board_select_n
      );

END STR;