input_latch_rtl.vhd

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LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;


ENTITY input_latch IS
   PORT( 
      n_ds0_int     : IN     std_logic;  -- n_ds0_int => VMEDS_L
      n_write       : IN     std_logic;
      vme_address   : IN     std_logic_vector (23 DOWNTO 1);
      address_ltchd : OUT    std_logic_vector (23 DOWNTO 1);
      n_write_ltchd : OUT    std_logic
   );
END input_latch ;

--------------------------------------------------------------------------------
architecture rtl of input_latch is
--------------------------------------------------------------------------------
-- ... to Latch VME inputs because some VME masters 
-- remove them before the cycle is over.
--
-- IPB 2005.
-- WTF : latches generate synthesis warnings: add an else clause to infer
-- FFs instead.

  signal address_ltchd_sig: std_logic_vector(23 downto 1);
  signal n_write_ltchd_sig: std_logic;
  
--------------------------------------------------------------------------------
begin

  address_ltchd<=address_ltchd_sig;
  n_write_ltchd<=n_write_ltchd_sig;
  
  latchproc: process (n_ds0_int, vme_address, n_write, address_ltchd_sig, n_write_ltchd_sig)
  begin
    if (n_ds0_int = '1') then        -- n_ds0_int => VMEDS_L
      address_ltchd_sig <= vme_address;  -- latch at n_ds0_int = '0'
      n_write_ltchd_sig <= n_write;      -- latch at n_ds0_int = '0'
    else
      address_ltchd_sig <= address_ltchd_sig;
      n_write_ltchd_sig <= n_write_ltchd_sig;
    end if;
  end process;

end architecture rtl;