glink_interface.vhd

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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;

entity glink_interface is
  port (
    CLK_40MHz         : in  std_logic;
     CLK_120MHz        : in  std_logic;
     RST               : in  std_logic;
     DAQ_IN            : in  std_logic_vector (19 DOWNTO 0);
    ROI_IN            : in  std_logic_vector (19 DOWNTO 0);
    DAQ_DAV           : in  std_logic;
    ROI_DAV           : in  std_logic;
     DAQ_BYTE          : OUT std_logic_vector (7 downto 0);
     ROI_BYTE          : OUT std_logic_vector (7 downto 0);
     DAQ_ENCODED_DIAG  : OUT std_logic_vector (23 downto 0);
     daq_byte_out      : OUT std_logic_vector (1 downto 0);
     byte_pos_out      : OUT std_logic_vector (5 downto 0);
     word_sel_out      : OUT std_logic_vector (1 downto 0);
     readout_rst_out   : OUT std_logic 
     
     );
end glink_interface;

architecture RTL of glink_interface is

component Glink_Encoder
port (
        Reset                       : in std_logic;                       -- reset          
        Clock                       : in std_logic;                           -- clock
        tx_in                       : in std_logic_vector(19 downto 0);   -- Input data
        TxData                      : in std_logic;                       -- DAV* pin
        TxCntl                      : in std_logic;                       -- CAV* pin (always disabled on CMM)
        tx_out                      : out std_logic_vector(23 downto 0);  -- Output data --it will be modified.
        TDisparity_Q                : out std_logic_vector(5 downto 0);   -- Debug ports
        RDPos_Q                 : out std_logic;                      -- Debug ports 
        RDNeg_Q                 : out std_logic                         -- Debug ports

     );
end component;  

-- constant definitions

constant zero_0 : std_logic := '0';

attribute keep : string;
-- signal definitions

signal RST_r : std_logic;
signal RST_synced : std_logic;
signal readout_rst    : std_logic := '0';

-- Circular 120 MHz readout buffers
-- new signal

type circbuf is array (0 to 8) of std_logic_vector (7 downto 0);
signal daq_buf        : circbuf;
signal roi_buf        : circbuf;
signal word_sel       : std_logic_vector(1 downto 0) :="00";

signal byte_pos : std_logic_vector(5 downto 0) := (others => '0');

-- G-link emulator signal

signal roi_encoded    : std_logic_vector(23 downto 0);
signal daq_encoded    : std_logic_vector(23 downto 0);

attribute keep of  RST_r :  signal is "TRUE";

begin  -- RTL

-- diagnostic only

DAQ_ENCODED_DIAG <= daq_encoded;
byte_pos_out <= byte_pos;
word_sel_out <= word_sel;
readout_rst_out <= readout_rst; 

roi_encoder : Glink_Encoder
  port map (
        Reset                =>     RST,
        Clock                =>     CLK_40MHz,                           
        tx_in                =>     ROI_IN,
        TxData              =>      ROI_DAV,
        TxCntl              =>      zero_0,
        tx_out           =>    roi_encoded,
        -- Debug ports:
        TDisparity_Q        =>    open, 
        RDPos_Q          =>    open,
        RDNeg_Q         =>    open

     );
      
daq_encoder : Glink_Encoder
  port map (
       Reset               =>       RST,
       Clock               =>       CLK_40MHz,                           
       tx_in               =>       DAQ_IN,
       TxData              =>       DAQ_DAV,
       TxCntl              =>       zero_0,
       tx_out          =>     daq_encoded ,
       -- Debug ports:
       TDisparity_Q    =>    open,  
       RDPos_Q         =>    open,
       RDNeg_Q            =>    open

    );

capture_buffer : process (clk_40MHz)

begin

if rising_edge (CLK_40MHz) then
  if word_sel = "00" then
  
  roi_buf(0) <= roi_encoded (7 downto 0);
  roi_buf(1) <= roi_encoded (15 downto 8);  
  roi_buf(2) <= roi_encoded (23 downto 16);

  daq_buf(0) <= daq_encoded (7 downto 0);
  daq_buf(1) <= daq_encoded (15 downto 8);  
  daq_buf(2) <= daq_encoded (23 downto 16);

  elsif word_sel = "01" then
    
  roi_buf(3) <= roi_encoded (7 downto 0);
  roi_buf(4) <= roi_encoded (15 downto 8);  
  roi_buf(5) <= roi_encoded (23 downto 16);

  daq_buf(3) <= daq_encoded (7 downto 0);
  daq_buf(4) <= daq_encoded (15 downto 8);  
  daq_buf(5) <= daq_encoded (23 downto 16);
  
  else
  
  roi_buf(6) <= roi_encoded (7 downto 0);
  roi_buf(7) <= roi_encoded (15 downto 8);  
  roi_buf(8) <= roi_encoded (23 downto 16);

  daq_buf(6) <= daq_encoded (7 downto 0);
  daq_buf(7) <= daq_encoded (15 downto 8);  
  daq_buf(8) <= daq_encoded (23 downto 16);
  
end if;
end if;
end process; -- capture buffer


reset_buffer_timing : process (CLK_40MHz)

begin

if rising_edge(CLK_40MHz) then 

  if RST_synced = '1' then
    readout_rst <= '1'; -- reset signal synchronous with the 40 MHz clock
  else 
    readout_rst <= '0';
  end if;

  RST_synced<=RST_r;
  RST_r<=RST;
  
end if;

end process; -- reset_buffer_timing

readout_buffer : process (CLK_120MHz)

variable phase : integer := 2;

begin

if rising_edge(CLK_120MHz) then

  if (readout_rst = '1') then
    phase := 1;
  elsif (phase = 8) then
    phase := 0;
  else  
    phase := phase + 1;
  end if;
 
  if (phase < 3) then 
    word_sel <= "10"; -- write to word 2 while reading from word 0
  elsif (phase > 5) then
    word_sel <= "01"; -- write to word 1 while reading from word 2
  else
     word_sel <= "00"; -- write to word 0 while reading from word 1
  end if;
  
  roi_byte <= roi_buf(phase);
  daq_byte <= daq_buf(phase);

    byte_pos <= "0000" & word_sel;

end if; -- clock 120 MHz

end process; -- readout_buffer
 
end RTL;