glink_interface Entity Reference

Inheritance diagram for glink_interface:

Entities
RTL	architecture

Libraries
ieee
UNISIM

Use Clauses
ieee.std_logic_1164.all
ieee.std_logic_unsigned.all
ieee.std_logic_arith.all
UNISIM.VCOMPONENTS.all

Ports
CLK_40MHz	in std_logic
CLK_120MHz	in std_logic
RST	in std_logic
DAQ_IN	in std_logic_vector ( 19 downto 0 )
ROI_IN	in std_logic_vector ( 19 downto 0 )
DAQ_DAV	in std_logic
ROI_DAV	in std_logic
DAQ_BYTE	out std_logic_vector ( 7 downto 0 )
ROI_BYTE	out std_logic_vector ( 7 downto 0 )
DAQ_ENCODED_DIAG	out std_logic_vector ( 23 downto 0 )
daq_byte_out	out std_logic_vector ( 1 downto 0 )
byte_pos_out	out std_logic_vector ( 5 downto 0 )
word_sel_out	out std_logic_vector ( 1 downto 0 )
readout_rst_out	out std_logic

Detailed Description

Definition at line 17 of file glink_interface.vhd.

Member Data Documentation

byte_pos_out out std_logic_vector ( 5 downto 0 )

Port

Definition at line 30 of file glink_interface.vhd.

CLK_120MHz in std_logic

Port

Definition at line 20 of file glink_interface.vhd.

CLK_40MHz in std_logic

Port

Definition at line 19 of file glink_interface.vhd.

DAQ_BYTE out std_logic_vector ( 7 downto 0 )

Port

Definition at line 26 of file glink_interface.vhd.

daq_byte_out out std_logic_vector ( 1 downto 0 )

Port

Definition at line 29 of file glink_interface.vhd.

DAQ_DAV in std_logic

Port

Definition at line 24 of file glink_interface.vhd.

DAQ_ENCODED_DIAG out std_logic_vector ( 23 downto 0 )

Port

Definition at line 28 of file glink_interface.vhd.

DAQ_IN in std_logic_vector ( 19 downto 0 )

Port

Definition at line 22 of file glink_interface.vhd.

ieee

Library

Definition at line 10 of file glink_interface.vhd.

ieee.std_logic_1164.all

Package

Definition at line 11 of file glink_interface.vhd.

ieee.std_logic_arith.all

Package

Definition at line 13 of file glink_interface.vhd.

ieee.std_logic_unsigned.all

Package

Definition at line 12 of file glink_interface.vhd.

readout_rst_out out std_logic

Port

Definition at line 32 of file glink_interface.vhd.

ROI_BYTE out std_logic_vector ( 7 downto 0 )

Port

Definition at line 27 of file glink_interface.vhd.

ROI_DAV in std_logic

Port

Definition at line 25 of file glink_interface.vhd.

ROI_IN in std_logic_vector ( 19 downto 0 )

Port

Definition at line 23 of file glink_interface.vhd.

RST in std_logic

Port

Definition at line 21 of file glink_interface.vhd.

UNISIM

Library

Definition at line 14 of file glink_interface.vhd.

UNISIM.VCOMPONENTS.all

Package

Definition at line 15 of file glink_interface.vhd.

word_sel_out out std_logic_vector ( 1 downto 0 )

Port

Definition at line 31 of file glink_interface.vhd.

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The documentation for this class was generated from the following file:

• Common/trunk/sources/glink_interface.vhd