RTL Architecture Reference

Processes
capture_buffer	( CLK_40MHz )
reset_buffer_timing	( CLK_40MHz )
readout_buffer	( CLK_120MHz )

Components
Glink_Encoder	<Entity Glink_Encoder>

Constants
zero_0	std_logic := ' 0 '

Types
circbuf	array ( 0 to 8 ) of std_logic_vector ( 7 downto 0 )

Signals
RST_r	std_logic
RST_synced	std_logic
readout_rst	std_logic := ' 0 '
daq_buf	circbuf
roi_buf	circbuf
word_sel	std_logic_vector ( 1 downto 0 ) := " 00 "
byte_pos	std_logic_vector ( 5 downto 0 ) := ( others = > ' 0 ' )
roi_encoded	std_logic_vector ( 23 downto 0 )
daq_encoded	std_logic_vector ( 23 downto 0 )

Attributes
keep	string
keep	RST_r : signal is " TRUE "

Instantiations
roi_encoder	Glink_Encoder <Entity Glink_Encoder>
daq_encoder	Glink_Encoder <Entity Glink_Encoder>

Detailed Description

Definition at line 37 of file glink_interface.vhd.

Member Function Documentation

capture_buffer

(

clk_40MHz

)

Definition at line 121 of file glink_interface.vhd.

readout_buffer (   CLK_120MHz   )

Process

Definition at line 180 of file glink_interface.vhd.

reset_buffer_timing (   CLK_40MHz   )

Process

Definition at line 161 of file glink_interface.vhd.

Member Data Documentation

byte_pos std_logic_vector ( 5 downto 0 ) := ( others = > ' 0 ' )

Signal

Definition at line 73 of file glink_interface.vhd.

circbuf array ( 0 to 8 ) of std_logic_vector ( 7 downto 0 )

Type

Definition at line 68 of file glink_interface.vhd.

daq_buf circbuf

Signal

Definition at line 69 of file glink_interface.vhd.

daq_encoded std_logic_vector ( 23 downto 0 )

Signal

Definition at line 78 of file glink_interface.vhd.

daq_encoder Glink_Encoder

Instantiation

Definition at line 106 of file glink_interface.vhd.

Glink_Encoder

Component

Definition at line 39 of file glink_interface.vhd.

keep string

Attribute

Definition at line 58 of file glink_interface.vhd.

keep RST_r : signal is " TRUE "

Attribute

Definition at line 80 of file glink_interface.vhd.

readout_rst std_logic := ' 0 '

Signal

Definition at line 63 of file glink_interface.vhd.

roi_buf circbuf

Signal

Definition at line 70 of file glink_interface.vhd.

roi_encoded std_logic_vector ( 23 downto 0 )

Signal

Definition at line 77 of file glink_interface.vhd.

roi_encoder Glink_Encoder

Instantiation

Definition at line 91 of file glink_interface.vhd.

RST_r std_logic

Signal

Definition at line 61 of file glink_interface.vhd.

RST_synced std_logic

Signal

Definition at line 62 of file glink_interface.vhd.

word_sel std_logic_vector ( 1 downto 0 ) := " 00 "

Signal

Definition at line 71 of file glink_interface.vhd.

zero_0 std_logic := ' 0 '

Constant

Definition at line 56 of file glink_interface.vhd.

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The documentation for this class was generated from the following file:

• Common/trunk/sources/glink_interface.vhd