glink_encoder.vhd

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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
 
entity Glink_Encoder is

PORT(
    Reset                       : in std_logic;         
    Clock                       : in std_logic;                         
            
    tx_in                       : in std_logic_vector(19 downto 0);
    TxData                 : in std_logic;  -- DAV pin, active high for this module
    TxCntl                 : in std_logic;  -- CAV pin  (Not used for CMX, not functional in this module)                   
                    
    tx_out                          : out std_logic_vector(23 downto 0);
    
    -- Debug outputs (kept for legacy purposes)
    TDisparity_Q                    : out std_logic_vector(5 downto 0); 
    RDPos_Q                         : out std_logic;
    RDNeg_Q                         : out std_logic 

    );
END Glink_Encoder;  

architecture rtl of Glink_Encoder  is



signal Flag             :  std_logic := '0';      -- Flagsel always zero
signal TDisparity       :  std_logic_vector(7 downto 0) := (others => '0');     

begin
    
-----------------------------------------------------------------------------------------------------------
--  Calculate accumulated disparity and produce correct output accordingly
----------------------------------------------------------------------------------------------------------- 

    process(Clock,Reset)
    variable tx_uninverted, tx_inverted : std_logic_vector(23 downto 0);
    variable ones : std_logic_vector(7 downto 0);
    
    begin
        if (Reset = '1') then
            Flag <= '0';   
            TDisparity <= (OTHERS => '0');
            tx_out <= x"000FFF";
            
        elsif rising_edge(Clock) then   
                  
        -- Construct inverted and non-inverted words

            if TxData = '0' then   -- Idle (send fill frames)
                tx_uninverted := "110000000000011111111111"; -- Idle Word 1a (C007FF)
                tx_inverted   := "110000000000000111111111"; -- Idle Word 1b (C001FF)
            else    -- DAV asserted (send data frame)
                                 Flag <= not (Flag);  -- toggle the Flag bit only when a data frame is sent
                                 if Flag = '0' then
                    tx_uninverted := "1011" & tx_in;
                    tx_inverted   := "0100" & not(tx_in);
                else
                    tx_uninverted := "1101" & tx_in;
                    tx_inverted   := "0010" & not(tx_in);
                end if;
            end if;

        -- calculate word disparity 

        ones := (OTHERS => '0');
        for i in 0 to 23 loop
            if (tx_uninverted(i) = '1') then
                ones := ones+1;
            end if; 
        end loop;

        if ones = x"0C" then
            tx_out <= tx_uninverted; -- If no disparity, send uninverted output
            TDisparity <= TDisparity; -- No change to total disparity
        elsif TDisparity(7) = '0' then -- Zero or positive total disparity
            if ones > x"0C" then
                tx_out <= tx_inverted; -- Positive word disparity, send inverted output
                TDisparity <= TDisparity - ones + x"0C";
            else
                tx_out <= tx_uninverted; -- negative word disparity, send uninverted output
                TDisparity <= TDisparity + ones - x"0C";
            end if;
        else -- Negative total disparity
            if ones > x"0C" then
                tx_out <= tx_uninverted; -- Positive word disparity, send uninverted output
                TDisparity <= TDisparity + ones - x"0C";
            else
                tx_out <= tx_inverted; -- Negative word disparity, send inverted output
                TDisparity <= TDisparity - ones + x"0C";
            end if;     
        end if; 

-- Output to legacy ports
            
        TDisparity_Q    <= TDisparity (5 downto 0);

        if ones > x"0C" then
            RDPos_Q <= '1';
        else
            RDPos_Q <= '0';
        end if;

        if ones < x"0C" then
            RDPos_Q <= '0';
        else
            RDPos_Q <= '1';
        end if;
                
    end if; -- Rising edge of Clock
    
    end process;    
                    
end;