rtl Architecture Reference

Processes
PROCESS_82	( Clock , Reset )

Signals
Flag	std_logic := ' 0 '
TDisparity	std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )

Detailed Description

Definition at line 34 of file glink_encoder.vhd.

Member Function Documentation

PROCESS_82 (   Clock ,   Reset   )

Process

Definition at line 47 of file glink_encoder.vhd.

Member Data Documentation

Flag std_logic := ' 0 '

Signal

Definition at line 38 of file glink_encoder.vhd.

TDisparity std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )

Signal

Definition at line 39 of file glink_encoder.vhd.

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The documentation for this class was generated from the following file:

• Common/trunk/sources/glink_encoder.vhd