Delay.vhd

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Delay is
  generic (
    del_length : integer := 2);
   port (
    undelayed_in         : in  std_logic;
    delayed_out        : out std_logic; 
    clk               : in std_logic);
end Delay;

architecture Behavioral of Delay is
  signal tmp : std_logic_vector(del_length downto 0);
  
  
begin


  gen_delay: for i_tick in tmp'high downto 1 generate

    process(clk)
    begin
      if rising_edge(clk) then
        tmp(i_tick)<=tmp(i_tick-1);
      end if;
    end process;

  end generate gen_delay;
  
  tmp(0)<=undelayed_in;
  
  delayed_out<=tmp(tmp'high);
  
end Behavioral;