daq_glink.vhd

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library ieee;
use ieee.std_logic_1164.all;
--use IEEE.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.ALL;

library unisim;
use unisim.vcomponents.all;



use work.CMXpackage.all;
use work.CMX_VME_defs.all;


entity daq_glink is
  port (

    data_in : in arr_96(19 downto 0); 
--    data_in       : in  std_logic_vector((data_width-1) downto 0);
--    orbit_counter : in  std_logic_vector(11 downto 0);
    bc_counter               : in unsigned(11 downto 0);
    l1a                      : in  std_logic;
    data_out                 : out std_logic_vector(19 downto 0);
    dav                      : out std_logic;
    clk4000                  : in  std_logic;
    clk4008                  : in  std_logic;
    reset                    : in  std_logic;
    RAM_global_offset        : in  unsigned(7 downto 0);
    RAM_rel_offsets          : in  arr_ctr_8bit(18 downto 0);
    nslices                  : in  unsigned(7 downto 0)
    );

end daq_glink;

architecture Behavioral of daq_glink is


-- signal and constans declarations

  signal data_in_reg : arr_96(19 downto 0);
  signal bc_counter_reg : unsigned(11 downto 0);
  
  signal dav_space      : std_logic_vector(8 downto 0);

  -- extended to maintain properly the parity bit attached to each single package
  constant slice_1   : std_logic_vector(8 downto 0):= "001100000";
  constant slice_3   : std_logic_vector(8 downto 0):= "100100010";
  constant slice_5   : std_logic_vector(8 downto 0):= "111100100";


  signal cur_wr_address : unsigned(7 downto 0); --the address the data
                                                --is being written to

  signal cur_wr_address_i : arr_ctr_8bit(19 downto 0);
  
  signal addr_rd_low : unsigned(7 downto 0);
                                        --this walks in sync with cur_wr_arddress
                                        -- cur_wr_address minus programmable offset minus nslices
  signal addr_rd_high: unsigned(7 downto 0);
                                        --upon reception of l1a this gets
                                        --locked to
                                        --cur_wr_address minus programmable offset plus nslices

  
    

  --WTF: BUG: --signal bc_counter_readout_uncorrected: unsigned(11 downto 0); --current
  --WTF: BUG:                                                               --bc_counter
  --WTF: BUG:                                                               --minus offset
  --WTF: BUG:                                                               --(not
  --WTF: BUG:                                                               --corrected for
  --WTF: BUG:                                                               --mod 3564 logic)

  signal bc_counter_readout: unsigned(11 downto 0); --after 3564 wrap around
                                                    --this is the bcid that
                                                    --will be appended to the
                                                    --sent data

  signal data_buffered_out_short: arr_96(19 downto 0);
  signal data_buffered_out: std_logic_vector(20*96-1 downto 0); --data read out
                                                                --from the
                                                                --scrolling
                                                                --memory which
                                                                --is then fed
                                                                --into fifo.

  signal data_fifo_out: std_logic_vector(20*96-1 downto 0); -- data from the
                                                            -- fifo to be
                                                            -- loaded onto
                                                            -- shift register
  
  

  component Readout_BUFFER_RAM is
    port (
      clka  : IN  STD_LOGIC;
      ena   : IN  STD_LOGIC;
      wea   : IN  STD_LOGIC_VECTOR(0 DOWNTO 0);
      addra : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
      dina  : IN  STD_LOGIC_VECTOR(95 DOWNTO 0);
      clkb  : IN  STD_LOGIC;
      addrb : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
      doutb : OUT STD_LOGIC_VECTOR(95 DOWNTO 0));
  end component Readout_BUFFER_RAM;
  

  component Readout_FIFO is
    port (
      rst    : IN  STD_LOGIC;
      wr_clk : IN  STD_LOGIC;
      rd_clk : IN  STD_LOGIC;
      din    : IN  STD_LOGIC_VECTOR(1919 DOWNTO 0);
      wr_en  : IN  STD_LOGIC;
      rd_en  : IN  STD_LOGIC;
      dout   : OUT STD_LOGIC_VECTOR(1919 DOWNTO 0);
      full   : OUT STD_LOGIC;
      empty  : OUT STD_LOGIC);
  end component Readout_FIFO;
  
  signal fifo_wr_en: std_logic;

  signal fifo_full :std_logic;
  signal fifo_empty : std_logic;
  
  -- signal read_next, read_next_d : std_logic;
  signal read_next : std_logic;

  type shift_reg_type is array (19 downto 0) of std_logic_vector(95 downto 0);  
  signal shift_reg : shift_reg_type;
  signal parity  : std_logic_vector(19 downto 0);
  signal frame_counter : std_logic_vector(dav_space'high downto 0):=(others => '0');


  -- control part
  signal rd_en, ena0, ena1 : std_logic:='0';
  signal dav_nd2,dav_nd1,dav_nd0 : std_logic:='0';
  signal ctrl_fsm : std_logic_vector(2 downto 0):=(others => '0');
  signal dav_down_nd2, dav_down_nd1,dav_down : std_logic;
  signal ena0_del0, ena0_del1 : std_logic;

begin


  --register input data and bcid to ease timing closure by local replication of
  --registers
  process(clk4008)
  begin
    if rising_edge(clk4008) then
      data_in_reg<=data_in;
      bc_counter_reg<=bc_counter;
    end if;
  end process;
  
  --buffer memories -store all event data in 256 event cycle
  mem_gen: for i_mem in 19 downto 0 generate

    gen_cur_wr_address_mem0: if i_mem=0 generate 
      cur_wr_address_i(i_mem)<=cur_wr_address;
    end generate gen_cur_wr_address_mem0;

    gen_cur_wr_address_mem_1_to_19: if i_mem/=0 generate 
      cur_wr_address_i(i_mem)<=cur_wr_address+RAM_rel_offsets(i_mem-1);
    end generate gen_cur_wr_address_mem_1_to_19;

    
      
    Readout_BUFFER_RAM_inst: entity work.Readout_BUFFER_RAM
      port map (
        clka   => clk4008,
        ena    => '1',
        wea(0)=> '1',
        addra  => std_logic_vector (cur_wr_address_i(i_mem)),
        dina   => data_in_reg (i_mem),
        clkb   => clk4008,
        addrb  => std_logic_vector (addr_rd_low),
        doutb  => data_buffered_out_short(i_mem));
    lower_rows: if i_mem /= 19 generate
      data_buffered_out((i_mem+1)*96-1 downto i_mem*96)<=data_buffered_out_short(i_mem);
    end generate lower_rows;
    upper_row: if i_mem=19 generate
      --leave space for the BCID and FIFO overflow
      data_buffered_out((i_mem+1)*96-1 downto i_mem*96+13)<=data_buffered_out_short(i_mem)(95 downto 13);
      data_buffered_out(i_mem*96+12)<=fifo_full;
      data_buffered_out((i_mem*96)+11 downto i_mem*96)<=std_logic_vector(bc_counter_readout);
    end generate upper_row; 
  end generate mem_gen;

  -- this process drives the advancing address and detects the l1a
  -- if l1a arrives the data is started to be loaded onto fifo
  -- the fifo_wr_en is asserted and then de-asserted when addresses high and
  -- low match
  process(clk4008, reset)
  begin
    if reset='1' then
      cur_wr_address<=to_unsigned(0,8);
      addr_rd_low<=to_unsigned(0,8);-- -offset-nslices;
      addr_rd_high<=to_unsigned(0,8);
      bc_counter_readout<=to_unsigned(0,12);
      fifo_wr_en<='0';
    elsif rising_edge(clk4008) then
      cur_wr_address<=cur_wr_address+1;
      addr_rd_low<=cur_wr_address-RAM_global_offset-nslices;
      if l1a='1' then
        fifo_wr_en<='1';
        addr_rd_high<=cur_wr_address-RAM_global_offset+nslices;
        if bc_counter_reg>RAM_global_offset then
          bc_counter_readout<=bc_counter_reg-RAM_global_offset-1;
        else
          bc_counter_readout<=to_unsigned(3563,12)-(resize(RAM_global_offset,12)-bc_counter_reg);
        end if;
        --WTF: BUG: bc_counter_readout_uncorrected<=bc_counter_reg-RAM_global_offset-1;
      --need to add here replacing part of the data with fixed BCID
      else
        if fifo_wr_en='1' and addr_rd_high=addr_rd_low then
          fifo_wr_en<='0';
        end if;
      end if;
    end if;
  end process;

  --WTF: BUG: bc_counter_readout<=bc_counter_readout_uncorrected - to_unsigned(3564,11) when bc_counter_readout_uncorrected>=3564 else bc_counter_readout_uncorrected;

  Readout_FIFO_inst: entity work.Readout_FIFO
    port map (
      rst     => reset,
      wr_clk  => clk4008,
      rd_clk  => clk4000,
      din     => data_buffered_out ,
      wr_en   => fifo_wr_en,
      rd_en   => rd_en,
      dout    => data_fifo_out,
      full    => fifo_full,
      empty   => fifo_empty);
  
  
  process (clk4000, reset)
  begin  -- process ADDR
    if reset = '1' then                 -- asynchronous reset (active high)
      ctrl_fsm <= (others => '0');
      dav_nd2 <= '0';
      dav_down_nd2 <= '0';
    elsif clk4000'event and clk4000 = '1' then  -- rising clock edge
      case ctrl_fsm is
        when "000" =>         
          if fifo_empty = '0' then   -- fifo is not empty
            ctrl_fsm <= "001";
          end if; 
        when "001" =>           
          dav_nd2 <= '1';         
          if frame_counter = "000000001" then
            ctrl_fsm <= "010";
           end if;           
        when "010" =>
          ctrl_fsm <= "011";
          dav_down_nd2 <= '1';            
        when "011" =>
          dav_down_nd2 <= '0';            
          dav_nd2 <= '0';
          ctrl_fsm <= "100";
        when "100" =>
          ctrl_fsm <= "000";  
        when others => 
          dav_down_nd2 <= '0';               
          dav_nd2 <= '0';
          ctrl_fsm <= "000";          
      end case;
    end if; 
  end process;
  
  process(clk4000)
  begin
    if (clk4000'event and clk4000 = '1') then
      if ctrl_fsm = "001" then 
        frame_counter <= std_logic_vector(unsigned(frame_counter)  - to_unsigned(1,9));                 
      else
        frame_counter <= dav_space;
      end if;
    end if;
  end process;

  dav_space <= slice_3 when std_logic_vector(nslices(1 downto 0))="01" else
               slice_5 when std_logic_vector(nslices(1 downto 0))="10" else
               slice_1;
  
--  dav_space <= slice_1 when nslices = "00" else  -- 1 slices
--               slice_3 when nslices = "01" else  -- 3 slices
--               slice_5 when nslices = "10";    -- 5 slices                
  
  
  
  SH_REG: process (clk4000, reset)
  begin  -- process SH_REG
    if reset = '1' then                 -- asynchronous reset (active high)
      shift_reg <= (others => (others => '0'));
      parity <= (others => '1');
    elsif clk4000'event and clk4000 = '1' then  -- rising clock edge
      for i in 0 to 19 loop   
        shift_reg(i) <= '0' & shift_reg(i)(95 downto 1);
      end loop;  -- i
      for i in 0 to 19 loop
        parity(i) <= parity(i) xor shift_reg(i)(0);
      end loop;              
        if read_next = '1' then
        for i in 0 to 19 loop     
          shift_reg(i) <= data_fifo_out(96*i+95 downto  96*i);
        end loop;
        parity <= (others => '1');
      end if;
    end if;
  end process SH_REG;
  
  DOUT: process (clk4000, reset)
  begin  -- process DOUT
    if reset = '1' then                 -- asynchronous reset (active low)
      data_out <= (others => '0');
      read_next <= '0';      
      rd_en <= '0';      
    elsif clk4000'event and clk4000 = '1' then  -- rising clock edge
      for i in 0 to 19 loop
        data_out(i) <= shift_reg(i)(0);
      end loop; 
      dav_nd1 <= dav_nd2;
        dav_nd0 <= dav_nd1;
        dav     <= dav_nd0; 

      dav_down_nd1 <= dav_down_nd2;
      dav_down <= dav_down_nd1;
                
        ena0_del0 <= ena0;
        ena0_del1 <= ena0_del0;

      if ctrl_fsm = "001" and fifo_empty = '0' and (unsigned(frame_counter) mod to_unsigned(97,9)) = 0 and 
        frame_counter /= dav_space  then
        ena0 <= '1';
      else
        ena0 <= '0';      
      end if;
      
      if fifo_empty = '0' and ctrl_fsm = "000" then
        ena1 <= '1';
      elsif ctrl_fsm = "001" then
        ena1 <= '0';
      end if;       
      
      rd_en <= ena0 or ena1;
      read_next <= rd_en;

      if dav_down = '1' or ena0_del1 = '1' then
        data_out <= parity;
      end if;              
      
    end if;
  end process DOUT;
  
  
end Behavioral;