Behavioral Architecture Reference

Processes
PROCESS_77	( clk4008 )
PROCESS_78	( clk4008 , reset )
PROCESS_79	( clk4000 , reset )
PROCESS_80	( clk4000 )
SH_REG	( clk4000 , reset )
DOUT	( clk4000 , reset )

Components
Readout_BUFFER_RAM
Readout_FIFO	<Entity Readout_FIFO>

Constants
slice_1	std_logic_vector ( 8 downto 0 ) := " 001100000 "
slice_3	std_logic_vector ( 8 downto 0 ) := " 100100010 "
slice_5	std_logic_vector ( 8 downto 0 ) := " 111100100 "

Types
shift_reg_type	array ( 19 downto 0 ) of std_logic_vector ( 95 downto 0 )

Signals
data_in_reg	arr_96 ( 19 downto 0 )
bc_counter_reg	unsigned ( 11 downto 0 )
dav_space	std_logic_vector ( 8 downto 0 )
cur_wr_address	unsigned ( 7 downto 0 )
cur_wr_address_i	arr_ctr_8bit ( 19 downto 0 )
addr_rd_low	unsigned ( 7 downto 0 )
addr_rd_high	unsigned ( 7 downto 0 )
bc_counter_readout	unsigned ( 11 downto 0 )
data_buffered_out_short	arr_96 ( 19 downto 0 )
data_buffered_out	std_logic_vector ( 20 * 96 - 1 downto 0 )
data_fifo_out	std_logic_vector ( 20 * 96 - 1 downto 0 )
fifo_wr_en	std_logic
fifo_full	std_logic
fifo_empty	std_logic
read_next	std_logic
shift_reg	shift_reg_type
parity	std_logic_vector ( 19 downto 0 )
frame_counter	std_logic_vector ( dav_space ' high downto 0 ) := ( others = > ' 0 ' )
rd_en	std_logic := ' 0 '
ena0	std_logic := ' 0 '
ena1	std_logic := ' 0 '
dav_nd2	std_logic := ' 0 '
dav_nd1	std_logic := ' 0 '
dav_nd0	std_logic := ' 0 '
ctrl_fsm	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
dav_down_nd2	std_logic
dav_down_nd1	std_logic
dav_down	std_logic
ena0_del0	std_logic
ena0_del1	std_logic

Instantiations
readout_buffer_ram_inst	work.readout_buffer_ram
readout_fifo_inst	Readout_FIFO <Entity Readout_FIFO>

Detailed Description

Definition at line 42 of file daq_glink.vhd.

Member Function Documentation

DOUT (   clk4000 ,   reset   )

Process

Definition at line 319 of file daq_glink.vhd.

PROCESS_77 (   clk4008   )

Process

Definition at line 153 of file daq_glink.vhd.

PROCESS_78	(		clk4008 ,
			reset
	)

Definition at line 199 of file daq_glink.vhd.

PROCESS_79	(		clk4000 ,
			reset
	)

Definition at line 243 of file daq_glink.vhd.

PROCESS_80 (   clk4000   )

Process

Definition at line 277 of file daq_glink.vhd.

SH_REG (   clk4000 ,   reset   )

Process

Definition at line 298 of file daq_glink.vhd.

Member Data Documentation

addr_rd_high unsigned ( 7 downto 0 )

Signal

Definition at line 66 of file daq_glink.vhd.

addr_rd_low unsigned ( 7 downto 0 )

Signal

Definition at line 63 of file daq_glink.vhd.

bc_counter_readout unsigned ( 11 downto 0 )

Signal

Definition at line 81 of file daq_glink.vhd.

bc_counter_reg unsigned ( 11 downto 0 )

Signal

Definition at line 48 of file daq_glink.vhd.

ctrl_fsm std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )

Signal

Definition at line 144 of file daq_glink.vhd.

cur_wr_address unsigned ( 7 downto 0 )

Signal

Definition at line 58 of file daq_glink.vhd.

cur_wr_address_i arr_ctr_8bit ( 19 downto 0 )

Signal

Definition at line 61 of file daq_glink.vhd.

data_buffered_out std_logic_vector ( 20 * 96 - 1 downto 0 )

Signal

Definition at line 87 of file daq_glink.vhd.

data_buffered_out_short arr_96 ( 19 downto 0 )

Signal

Definition at line 86 of file daq_glink.vhd.

data_fifo_out std_logic_vector ( 20 * 96 - 1 downto 0 )

Signal

Definition at line 94 of file daq_glink.vhd.

data_in_reg arr_96 ( 19 downto 0 )

Signal

Definition at line 47 of file daq_glink.vhd.

dav_down std_logic

Signal

Definition at line 145 of file daq_glink.vhd.

dav_down_nd1 std_logic

Signal

Definition at line 145 of file daq_glink.vhd.

dav_down_nd2 std_logic

Signal

Definition at line 145 of file daq_glink.vhd.

dav_nd0 std_logic := ' 0 '

Signal

Definition at line 143 of file daq_glink.vhd.

dav_nd1 std_logic := ' 0 '

Signal

Definition at line 143 of file daq_glink.vhd.

dav_nd2 std_logic := ' 0 '

Signal

Definition at line 143 of file daq_glink.vhd.

dav_space std_logic_vector ( 8 downto 0 )

Signal

Definition at line 50 of file daq_glink.vhd.

ena0 std_logic := ' 0 '

Signal

Definition at line 142 of file daq_glink.vhd.

ena0_del0 std_logic

Signal

Definition at line 146 of file daq_glink.vhd.

ena0_del1 std_logic

Signal

Definition at line 146 of file daq_glink.vhd.

ena1 std_logic := ' 0 '

Signal

Definition at line 142 of file daq_glink.vhd.

fifo_empty std_logic

Signal

Definition at line 130 of file daq_glink.vhd.

fifo_full std_logic

Signal

Definition at line 129 of file daq_glink.vhd.

fifo_wr_en std_logic

Signal

Definition at line 127 of file daq_glink.vhd.

frame_counter std_logic_vector ( dav_space ' high downto 0 ) := ( others = > ' 0 ' )

Signal

Definition at line 138 of file daq_glink.vhd.

parity std_logic_vector ( 19 downto 0 )

Signal

Definition at line 137 of file daq_glink.vhd.

rd_en std_logic := ' 0 '

Signal

Definition at line 142 of file daq_glink.vhd.

read_next std_logic

Signal

Definition at line 133 of file daq_glink.vhd.

Readout_BUFFER_RAM

Component

Definition at line 101 of file daq_glink.vhd.

readout_buffer_ram_inst work.readout_buffer_ram

Instantiation

Definition at line 174 of file daq_glink.vhd.

Readout_FIFO

Component

Definition at line 114 of file daq_glink.vhd.

readout_fifo_inst Readout_FIFO

Instantiation

Definition at line 230 of file daq_glink.vhd.

shift_reg shift_reg_type

Signal

Definition at line 136 of file daq_glink.vhd.

shift_reg_type array ( 19 downto 0 ) of std_logic_vector ( 95 downto 0 )

Type

Definition at line 135 of file daq_glink.vhd.

slice_1 std_logic_vector ( 8 downto 0 ) := " 001100000 "

Constant

Definition at line 53 of file daq_glink.vhd.

slice_3 std_logic_vector ( 8 downto 0 ) := " 100100010 "

Constant

Definition at line 54 of file daq_glink.vhd.

slice_5 std_logic_vector ( 8 downto 0 ) := " 111100100 "

Constant

Definition at line 55 of file daq_glink.vhd.

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The documentation for this class was generated from the following file:

• Common/trunk/sources/daq_glink.vhd