Readout_FIFO.vhd

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LIBRARY ieee ;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;

use work.CMXpackage.all; 


entity Readout_FIFO is
  port(
    rst : IN STD_LOGIC;
    wr_clk : IN STD_LOGIC;
    rd_clk : IN STD_LOGIC;
    din : IN STD_LOGIC_VECTOR(1919 DOWNTO 0);
    wr_en : IN STD_LOGIC;
    rd_en : IN STD_LOGIC;
    dout : OUT STD_LOGIC_VECTOR(1919 DOWNTO 0);
    full : OUT STD_LOGIC;
    empty : OUT STD_LOGIC
    );

-- Declarations

end Readout_FIFO ;
--------------------------------------------------------------------------------
ARCHITECTURE RTL OF Readout_FIFO IS
--------------------------------------------------------------------------------

  component Readout_half_FIFO is
    port (
      rst    : IN  STD_LOGIC;
      wr_clk : IN  STD_LOGIC;
      rd_clk : IN  STD_LOGIC;
      din    : IN  STD_LOGIC_VECTOR(959 DOWNTO 0);
      wr_en  : IN  STD_LOGIC;
      rd_en  : IN  STD_LOGIC;
      dout   : OUT STD_LOGIC_VECTOR(959 DOWNTO 0);
      full   : OUT STD_LOGIC;
      empty  : OUT STD_LOGIC);
  end component Readout_half_FIFO;

  signal din_1 : STD_LOGIC_VECTOR(959 DOWNTO 0);
  signal din_2 : STD_LOGIC_VECTOR(959 DOWNTO 0);

  signal dout_1 : STD_LOGIC_VECTOR(959 DOWNTO 0);
  signal dout_2 : STD_LOGIC_VECTOR(959 DOWNTO 0);
  
  signal full_1 : STD_LOGIC;
  signal full_2 : STD_LOGIC;      

  signal empty_1 : STD_LOGIC;
  signal empty_2 : STD_LOGIC;      
  
--------------------------------------------------------------------------------
BEGIN

  Readout_half_FIFO_inst_1: entity work.Readout_half_FIFO
    port map (
      rst     => rst,
      wr_clk  => wr_clk,
      rd_clk  => rd_clk,
      din     => din_1,
      wr_en   => wr_en,
      rd_en   => rd_en,
      dout    => dout_1,
      full    => full_1,
      empty   => empty_1);

  Readout_half_FIFO_inst_2: entity work.Readout_half_FIFO
    port map (
      rst     => rst,
      wr_clk  => wr_clk,
      rd_clk  => rd_clk,
      din     => din_2,
      wr_en   => wr_en,
      rd_en   => rd_en,
      dout    => dout_2,
      full    => full_2,
      empty   => empty_2);
  

  dout<=dout_2 & dout_1;
  din_1<=din(959 downto 0);
  din_2<=din(1919 downto 960);

  full<=full_1 or full_2;

  empty<= empty_1 and empty_2;

  

END RTL;