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RTL Architecture Reference

Components

Readout_half_FIFO 

Signals

din_1  STD_LOGIC_VECTOR ( 959 downto 0 )
din_2  STD_LOGIC_VECTOR ( 959 downto 0 )
dout_1  STD_LOGIC_VECTOR ( 959 downto 0 )
dout_2  STD_LOGIC_VECTOR ( 959 downto 0 )
full_1  STD_LOGIC
full_2  STD_LOGIC
empty_1  STD_LOGIC
empty_2  STD_LOGIC

Instantiations

readout_half_fifo_inst_1  work.readout_half_fifo
readout_half_fifo_inst_2  work.readout_half_fifo

Detailed Description

Definition at line 30 of file Readout_FIFO.vhd.

Member Data Documentation

din_1 STD_LOGIC_VECTOR ( 959 downto 0 )
Signal

Definition at line 46 of file Readout_FIFO.vhd.

din_2 STD_LOGIC_VECTOR ( 959 downto 0 )
Signal

Definition at line 47 of file Readout_FIFO.vhd.

dout_1 STD_LOGIC_VECTOR ( 959 downto 0 )
Signal

Definition at line 49 of file Readout_FIFO.vhd.

dout_2 STD_LOGIC_VECTOR ( 959 downto 0 )
Signal

Definition at line 50 of file Readout_FIFO.vhd.

empty_1 STD_LOGIC
Signal

Definition at line 55 of file Readout_FIFO.vhd.

empty_2 STD_LOGIC
Signal

Definition at line 56 of file Readout_FIFO.vhd.

full_1 STD_LOGIC
Signal

Definition at line 52 of file Readout_FIFO.vhd.

full_2 STD_LOGIC
Signal

Definition at line 53 of file Readout_FIFO.vhd.

Readout_half_FIFO
Component

Definition at line 33 of file Readout_FIFO.vhd.

readout_half_fifo_inst_1 work.readout_half_fifo
Instantiation

Definition at line 61 of file Readout_FIFO.vhd.

readout_half_fifo_inst_2 work.readout_half_fifo
Instantiation

Definition at line 73 of file Readout_FIFO.vhd.

The documentation for this class was generated from the following file: