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parity_gen.vhd
Go to the documentation of this file.
1
13
14
LIBRARY
ieee
;
15
USE
ieee
.std_logic_1164.
all
;
16
USE
ieee
.numeric_std.
all
;
17
18
ENTITY
parity_gen
IS
19
GENERIC
(
20
width
:
integer
:=
60
21
)
;
22
PORT
(
23
din
:
IN
std_logic_vector
(
width
-
1
downto
0
)
;
24
parity
:
OUT
std_logic
25
)
;
26
27
-- Declarations
28
29
END
parity_gen
;
30
31
-- renoir interface_end
32
ARCHITECTURE
rtl
OF
parity_gen
IS
33
--------------------------------------------------------------------------------
34
-- Calculate the (odd) parity of incoming data and output result.
35
--
36
--------------------------------------------------------------------------------
37
BEGIN
38
39
parity_check
:
process
(
din
)
40
variable
iparity
:
std_logic
;
41
begin
42
iparity
:=
'
1
'
;
-- odd parity
43
for
i
in
0
to
(
width
-
1
)
loop
44
iparity
:=
iparity
xor
din
(
i
)
;
45
end
loop
;
46
parity
<=
iparity
;
47
end
process
;
48
49
50
END
rtl
;
parity_gen
Definition:
parity_gen.vhd:18
parity_gen.rtl.parity_check
parity_checkdin
Definition:
parity_gen.vhd:39
parity_gen.parity
out paritystd_logic
Definition:
parity_gen.vhd:24
PARITY_CALC.IEEE
_library_ IEEEIEEE
Definition:
PARITY_CALC.vhd:11
parity_gen.width
widthinteger :=60
Definition:
parity_gen.vhd:20
parity_gen.din
in dinstd_logic_vector (width - 1 downto 0)
Definition:
parity_gen.vhd:23
Common
trunk
sources
parity_gen.vhd
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