PARITY_CALC.vhd

Go to the documentation of this file.

----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.REDUCE_PKG.ALL;

library work;
use work.CMXpackage.all;


-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity PARITY_CALC is
   port (
    DATA         : in  std_logic_vector(numbitsinchan - 1 downto 0);
    PARITY       : out std_logic);
end PARITY_CALC;

architecture Behavioral of PARITY_CALC is
  signal tmp : std_logic_vector(numbitsinchan - 1 downto 0);  
  
begin

  tmp(0)<=DATA(0);
  xor_gen: for bitnum in 1 to (numbitsinchan-1) generate
    tmp(bitnum) <= DATA(bitnum) xor tmp(bitnum-1);
  end generate xor_gen;
  PARITY<=tmp(numbitsinchan-1);

  --PARITY<=xor_reduce(DATA);
  
end Behavioral;