CRC_CHECK.vhd

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

library work;
use work.CMXpackage.all;


-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity CRC_CHECK is
   port (
    DATA_in          : in  std_logic_vector(15 downto 0);
    CRC_ERR          : out  std_logic;
    clk              : in std_logic;
    rx_subtick_counter  : in unsigned(2 downto 0));
end CRC_CHECK;

architecture Behavioral of CRC_CHECK is

  attribute keep_hierarchy : string;
  
  signal b0, b1 : std_logic_vector(7 downto 0);
  signal r0, r1, r2, r3, r4, r5, r6, r4_reg, r5_reg : std_logic_vector(11 downto 0);  
                                        -- crc register at varoius stages of the computation

  signal rx_subtick_counter_reg : unsigned(2 downto 0);

  --signal or_all_r6 : std_logic;
  

--  component crc_lut
--    port (
--      addr : in  std_logic_vector(7 downto 0);
--      data : out std_logic_vector(11 downto 0));
--  end component;
--

  --component or_all
  --  generic (
  --    numbits : integer);
  --  port (
  --    DATA   : in  std_logic_vector(numbits - 1 downto 0);
  --    or_all : out std_logic);
  --end component;
  
  COMPONENT crc_distmem
  PORT (
    a : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
    spo : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
  );
  END COMPONENT;

  attribute keep_hierarchy of Behavioral : architecture is "TRUE";
  
begin

  b0<=DATA_in(7 downto 0);
  b1<=DATA_in(15 downto 8);

  r1(11 downto 8)<=r0(3 downto 0);
  r1(7 downto 0)<=b1;

--  lut_0: crc_lut
--    port map (
--        addr => r0(11 downto 4),
--        data => r2);
--

  lut_0: crc_distmem
    port map (
        a    => r0(11 downto 4),
        spo  => r2);
  
  r3<=r1 xor r2;

  r4(11 downto 8)<=r3(3 downto 0);
  r4(7 downto 0)<=b0;

--  lut_1: crc_lut
--    port map (
--        addr => r3(11 downto 4),
--        data => r5);
--

  lut_1: crc_distmem
    port map (
        a    => r3(11 downto 4),
        spo  => r5);
  
  r6<= r5 xor r4;

  --or_all_1: or_all
  --  generic map (
  --    numbits => 12)
  --  port map (
  --    DATA   => r6,
  --    or_all => or_all_r6);

  process (clk)
  begin  -- process
    if rising_edge(clk) then  -- rising clock edge

      if rx_subtick_counter=to_unsigned(0,3) then
        r0<=(others=>'0');
      else
        r0<=r6;
      end if;

      if rx_subtick_counter_reg=to_unsigned(0,3) then
        if r5_reg=r4_reg then --r6="000000000000" then
          CRC_ERR<='0';
        else
          CRC_ERR<='1';
        end if;
      end if;
      
      rx_subtick_counter_reg<=rx_subtick_counter;
      r5_reg<=r5;
      r4_reg<=r4;
      
    end if;
  end process;
  
end Behavioral;