Behavioral Architecture Reference

Processes
PROCESS_76	( clk )

Components
crc_distmem

Signals
b0	std_logic_vector ( 7 downto 0 )
b1	std_logic_vector ( 7 downto 0 )
r0	std_logic_vector ( 11 downto 0 )
r1	std_logic_vector ( 11 downto 0 )
r2	std_logic_vector ( 11 downto 0 )
r3	std_logic_vector ( 11 downto 0 )
r4	std_logic_vector ( 11 downto 0 )
r5	std_logic_vector ( 11 downto 0 )
r6	std_logic_vector ( 11 downto 0 )
r4_reg	std_logic_vector ( 11 downto 0 )
r5_reg	std_logic_vector ( 11 downto 0 )
rx_subtick_counter_reg	unsigned ( 2 downto 0 )

Attributes
keep_hierarchy	string
keep_hierarchy	Behavioral : architecture is " TRUE "

Instantiations
lut_0	crc_distmem
lut_1	crc_distmem

Detailed Description

Definition at line 36 of file CRC_CHECK.vhd.

Member Function Documentation

PROCESS_76

(

clk

)

Definition at line 117 of file CRC_CHECK.vhd.

Member Data Documentation

b0 std_logic_vector ( 7 downto 0 )

Signal

Definition at line 40 of file CRC_CHECK.vhd.

b1 std_logic_vector ( 7 downto 0 )

Signal

Definition at line 40 of file CRC_CHECK.vhd.

crc_distmem

Component

Definition at line 64 of file CRC_CHECK.vhd.

keep_hierarchy string

Attribute

Definition at line 38 of file CRC_CHECK.vhd.

keep_hierarchy Behavioral : architecture is " TRUE "

Attribute

Definition at line 71 of file CRC_CHECK.vhd.

lut_0 crc_distmem

Instantiation

Definition at line 87 of file CRC_CHECK.vhd.

lut_1 crc_distmem

Instantiation

Definition at line 103 of file CRC_CHECK.vhd.

r0 std_logic_vector ( 11 downto 0 )

Signal

Definition at line 41 of file CRC_CHECK.vhd.

r1 std_logic_vector ( 11 downto 0 )

Signal

Definition at line 41 of file CRC_CHECK.vhd.

r2 std_logic_vector ( 11 downto 0 )

Signal

Definition at line 41 of file CRC_CHECK.vhd.

r3 std_logic_vector ( 11 downto 0 )

Signal

Definition at line 41 of file CRC_CHECK.vhd.

r4 std_logic_vector ( 11 downto 0 )

Signal

Definition at line 41 of file CRC_CHECK.vhd.

r4_reg std_logic_vector ( 11 downto 0 )

Signal

Definition at line 41 of file CRC_CHECK.vhd.

r5 std_logic_vector ( 11 downto 0 )

Signal

Definition at line 41 of file CRC_CHECK.vhd.

r5_reg std_logic_vector ( 11 downto 0 )

Signal

Definition at line 41 of file CRC_CHECK.vhd.

r6 std_logic_vector ( 11 downto 0 )

Signal

Definition at line 41 of file CRC_CHECK.vhd.

rx_subtick_counter_reg unsigned ( 2 downto 0 )

Signal

Definition at line 44 of file CRC_CHECK.vhd.

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The documentation for this class was generated from the following file:

• Common/trunk/sources/CRC_CHECK.vhd