9 USE ieee.std_logic_1164.
all;
12 --------------------------------------------------------------------------------
14 --------------------------------------------------------------------------------
435 ia_vme: ; -- VME location
436 addr_vme: (
15 downto 0); -- VME address
bus
437 ncs: ; -- chip
select, active low
438 rd_nwr: )
-- strobe, active high
440 return ;
-- read enable for location ia_vme
444 ia_vme: ; -- VME location
445 addr_vme: (
15 downto 0); -- VME address
bus
446 ncs: ; -- chip
select, active low
447 rd_nwr: )
-- strobe, active high
449 return ;
-- write enable for location ia_vme
456 --------------------------------------------------------------------------------
458 --------------------------------------------------------------------------------
459 --------------------------------------------------------------------------------
465 ia_vme: ; -- VME location
466 addr_vme: (
15 downto 0); -- VME address
bus
467 ncs: ; -- chip
select, active low
468 rd_nwr: )
-- 1=read, 0=write
470 return is -- read enable for location ia_vme
473 variable iaddr_vme:
range 0 to 65535;
-- 16-bit address
476 iaddr_vme := to_integer
((addr_vme
));
477 if (iaddr_vme = ia_vme/
2) and (ncs = '
0'
) and (rd_nwr = '
1'
) then
490 ia_vme: ; -- VME location
491 addr_vme: (
15 downto 0); -- VME address
bus
492 ncs: ; -- chip
select, active low
493 rd_nwr: )
-- 1=read, 0=write
495 return is -- write enable for location ia_vme
498 variable iaddr_vme:
range 0 to 65535;
-- 16-bit address
501 iaddr_vme := to_integer
((addr_vme
));
502 if (iaddr_vme = ia_vme/
2) and (ncs = '
0'
) and (rd_nwr = '
0'
) then
integer :=16#120C# ADDR_REG_RO_INPUT_SPY_MEM_SYSTEM_STATUS
integer :=16#15AA# ADDR_REG_RO_SUM_ET_COUNTER
8 32-bit sum ET threshold counters, 16 adresses, last one 15C8
integer :=16#0104# ADDR_REG_RO_backplane_forward
integer :=16#0100# ADDR_REG_RO_test
test RO register
integer :=16#0560# ADDR_REG_RO_IDELAYCTRL_WAS_RST
states if IDELAYCTRL has been reset
integer :=16#1250# ADDR_REG_RO_INPUT_SPY_MEM_SYSTEM_NOERROR_COUNTER
integer :=16#12FE# ADDR_REG_RO_RTM_SPY_SYSTEMDS2_MEM_CHECK_ERROR
integer :=16#1A2E# ADDR_REG_RW_MISS_E_RES_THR_BLOCK
8 31-bit MISS_E_RES THRESHOLDS, 16 address, last one 1A4C
integer :=16#12DA# ADDR_REG_RW_RTM_SPY_SYSTEM_MEM_START_ADDRESS
one register each for the start adresses for the system and ds2 rams
integer :=16#1A0E# ADDR_REG_RW_MISS_E_THR_BLOCK
8 31-bit MISS_E THRESHOLDS, 16 address, last one 1A2C
integer :=16#1AFE# ADDR_REG_RO_CLOCK_DIFF_DETECT_COUNTER
integer :=16#11F8# ADDR_REG_RW_DAQ_RAM_OFFSET
integer :=16#120E# ADDR_REG_RW_INPUT_SPY_MEM_SYSTEM_START_ADDRESS
one 8-bit words (upper 8 bits unused)
integer :=16#0102# ADDR_REG_RW_test
test RW register
std_logic_vector (3 downto 0) :="0001" CONST_DPR_CONTROL_SPY
integer :=16#0568# ADDR_REG_RW_TOPOTR_GTX_RESET
TOPO TR GTX RX (bit 0) TX (bit 1) reset.
integer :=16#166A# ADDR_REG_RO_PRESENCE_COUNTER
224 32-bit counters, 448 addresses, last one is 19EA
integer :=16#1AAE# ADDR_REG_RW_T_MISS_E_MAX_PARAM_BLOCK
8 31-bit T_MISS_E_MAX PARAM, 16 address, last one 1ACC
integer :=16#1AEE# ADDR_REG_RW_XS_B2_PARAM_BLOCK
8 15-bit XS_B PARAM, 8 address last one 1AFC
integer :=16#1316# ADDR_REG_RO_CLOCK_MANAGER_STATUS
PLL status (bit 0 is DS1 MMCM lock and bit 1 is for DS2 MMCM)
integer :=16#0144# ADDR_REG_RW_IDELAY_BACKPLANE
400 delay values last address is 16#0462#
integer :=16#14BA# ADDR_REG_RO_MULT_TOTAL_COUNTER
25 32-bit global rate counters (50 addresses), last one is 151C
integer :=16#1292# ADDR_REG_RW_CTP_OUTPUT_COUNTER_RESET
integer :=16#12D0# ADDR_REG_RW_RTM_SPY_SYSTEM_MEM_CONTROL
std_logic_vector (2 downto 0) :="101" CONST_DPR_STATUS_WRITE
integer :=16#12AE# ADDR_REG_RW_RTM_INPUT_COUNTER_RESET
reset for the RTM input module counters
integer :=16#04B6# ADDR_REG_RW_INPUT_SPY_MEM_SOURCE_CONTROL
control and status words with states defined below
integer :=16#1318# ADDR_REG_RW_DELAY_INPUT_DATA_ADDER
Delay for the input adder data.
integer :=16#04A8# ADDR_REG_RW_COUNTER_RESET
counter reset - resets counters of events and errors
integer :=16#12C8# ADDR_REG_RW_RTM_SPY_SYSTEM_MEM_WORD
same for the system RTM spies
integer :=16#12F2# ADDR_REG_RO_RTM_SPY_SOURCE_MEM_CHECK_ERROR
integer :=16#12AA# ADDR_REG_RO_CTP_SPY_MEM_NOERROR_COUNTER
integer :=16#15A8# ADDR_REG_RW_BC_RESET_ERROR_COUNTER_RESET
hold bit 0 high to reset the BCRESET error counter
integer :=16#055e# ADDR_REG_RO_IDELAYCTRL_RST
current IDELAYCTRL reset status
integer :=16#19EC# ADDR_REG_RW_DISABLE_OVERFLOW_MASK
integer :=16#19EE# ADDR_REG_RO_SYSMON_DATA_BLOCK
reserve 16 addresses for the sysmon, in first implementation 15 are used
integer :=16#162A# ADDR_REG_RO_SUM_ET_WEIGHTED_COUNTER
8 32-bit weighted/restricted sum ET threshold counters, 16 adresses, last one 1648 ...
integer :=16#055a# ADDR_REG_RW_CLOCK_MANAGER_RESET
integer :=16#1ADE# ADDR_REG_RW_T_SUM_E_MAX_PARAM_BLOCK
8 15-bit T_SUM_E_MAX PARAM, 8 address, last one 1AEC
integer :=16#11FA# ADDR_REG_RW_BCID_RESET_VAL
what is the value of the BCID we are get when the BC reset is received
integer :=16#1A5E# ADDR_REG_RW_SUM_ET_RES_THR_BLOCK
8 15-bit SUM_ET_RES THRESHOLDS, 8 address, last one 1A6C
integer :=16#15A6# ADDR_REG_RO_BC_RESET_ERROR_COUNTER
std_logic vme_wenia_vme,addr_vme,ncs,rd_nwr,
integer :=16#1386# ADDR_REG_RO_DAQ_ROI_STATUS
integer :=16#135E# ADDR_REG_RW_SUMET_MASK
mask for the restricted range sum ET
integer :=16#138E# ADDR_REG_RW_RATE_COUNTER_RESET
bit 0 set resets (and holds reset) the rate counters
integer :=16#1338# ADDR_REG_RW_DAQ_RAM_RELATIVE_OFFSET
integer :=16#138A# ADDR_REG_RO_TOPOTR_GTX_STATUS
bit 0 gives status of RX; bit 1 gives status of TX
integer :=16#0468# ADDR_REG_RO_PARITY_ERROR_COUNTER
integer :=16#04B8# ADDR_REG_RO_INPUT_SPY_MEM_SOURCE_STATUS
integer :=16#1ACE# ADDR_REG_RW_T_SUM_E_MIN_PARAM_BLOCK
8 15-bit T_SUM_E_MIN PARAM, 8 address, last one 1ADC
integer :=16#04AA# ADDR_REG_RW_INPUT_SPY_MEM_SOURCE_WORD
six consecutive addresses ending at 4B4
integer :=16#5000# ADDR_REG_RO_VERSION_COMMON
version registers
std_logic_vector (3 downto 0) :="0011" CONST_DPR_CONTROL_VERIFY
integer :=16#129E# ADDR_REG_RO_CTP_SPY_MEM_STATUS
status word for the CTP spy memory
integer :=16#1210# ADDR_REG_RO_INPUT_SPY_MEM_SYSTEM_CHECK_ERROR
integer :=16#12A0# ADDR_REG_RW_CTP_SPY_MEM_START_ADDRESS
start address for the CTP Spy memory
integer :=16#131E# ADDR_REG_RW_RTM_OUTPUT_SPY_SYSTEM_MEM_WORD
std_logic_vector (2 downto 0) :="110" CONST_DPR_STATUS_READ
std_logic vme_renia_vme,addr_vme,ncs,rd_nwr,
integer :=16#1B7E# ADDR_REG_RO_CLOCK_DIFF_RATCHET_UP_COUNTER
integer :=16#1326# ADDR_REG_RW_RTM_OUTPUT_SPY_SYSTEM_MEM_CONTROL
output RTM spy control and status
integer :=16#12D2# ADDR_REG_RO_RTM_SPY_SYSTEM_MEM_STATUS
integer :=16#1336# ADDR_REG_RW_RTM_OUTPUT_SPY_SYSTEM_MEM_START_ADDRESS
start address for the RTM spy memory
integer :=16#1294# ADDR_REG_RW_CTP_SPY_MEM_WORD
integer :=16#12B8# ADDR_REG_RW_RTM_SPY_SOURCE_MEM_CONTROL
control
integer :=16#11F6# ADDR_REG_RW_DAQ_SLICE
integer :=16#160A# ADDR_REG_RO_MISSING_ET_SIGN_COUNTER
8 32-bit missing ET significance threshold counters, 16 adresses, last one 1628
integer :=16#0566# ADDR_REG_RW_CTP_TESTER_DATA_SELECT
integer :=16#12BA# ADDR_REG_RO_RTM_SPY_SOURCE_MEM_STATUS
status
integer :=16#132A# ADDR_REG_RO_RTM_OUTPUT_SPY_SYSTEM_MEM_CHECK_ERROR
integer :=16#13F8# ADDR_REG_RO_MULT_REMOTE_COUNTER
integer :=16#151E# ADDR_REG_RO_TOB_COUNTER
16 32-bit tob counters (32 adresses), last one is 155C
integer :=16#0562# ADDR_REG_RW_INPUT_MOD_RESET
async register for controlling the reset of the input module
integer :=16#12E6# ADDR_REG_RO_RTM_PARITY_ERROR_COUNTER
std_logic_vector (2 downto 0) :="011" CONST_DPR_STATUS_WAIT_READ
integer :=16#131C# ADDR_REG_RW_RTM_OUTPUT_COUNTER_RESET
error counter reset register for the RTM output module
integer :=16#120A# ADDR_REG_RW_INPUT_SPY_MEM_SYSTEM_CONTROL
control and status words with states defined below
integer :=16#1B3E# ADDR_REG_RO_CLOCK_DIFF_DURATION_COUNTER
integer :=16#1384# ADDR_REG_RW_RTM_INPUT_CHANNEL_MASK
mask for the RTM inputs.
integer :=16#4998# ADDR_REG_RO_CMX_FLAVOR
integer :=16#12C6# ADDR_REG_RO_RTM_SPY_SYSTEMDS2_MEM_STATUS
integer :=16#1A8E# ADDR_REG_RW_T_MISS_E_MIN_PARAM_BLOCK
8 31-bit T_MISS_E_MIN PARAM, 16 address, last one 1AAC
integer :=16#12A2# ADDR_REG_RO_CTP_SPY_MEM_CHECK_ERROR
integer :=16#1A6E# ADDR_REG_RW_XS_T2_A2_THR_BLOCK
8 31-bit XS_T2_A2 THRESHOLDS, 16 address, last one 1A8C
integer :=16#1382# ADDR_REG_RW_QUIET_FORCE
integer :=16#12B0# ADDR_REG_RW_RTM_SPY_SOURCE_MEM_WORD
std_logic vme_renia_vme,addr_vme,ncs,rd_nwr,
integer :=16#1290# ADDR_REG_RW_SPY_MEM_WRITE_INHIBIT
integer :=16#04BA# ADDR_REG_RW_INPUT_SPY_MEM_SOURCE_START_ADDRESS
16 9-bit words (upper 7 bits unused), ending address 4D8
std_logic_vector (2 downto 0) :="001" CONST_DPR_STATUS_NORMAL
integer :=16#12C4# ADDR_REG_RW_RTM_SPY_SYSTEMDS2_MEM_CONTROL
integer :=16#1360# ADDR_REG_RW_MISSET_MASK
mask for the restricted range missing ET
integer :=16#1388# ADDR_REG_RW_DAQ_ROI_GTX_RESET
bit 0 reset DAQ, bit 1 resets ROI GTX (should be done at the same time)
integer :=16#1BBE# ADDR_REG_RO_CLOCK_DIFF_RATCHET_DOWN_COUNTER
integer :=16#0570# ADDR_REG_RW_TX_POLARITY
3 consecutive addresses for the TX polarity
integer :=16#11FC# ADDR_REG_RW_DAQ_ROI_RESET
the LSB of this will cause the DAQ machinery to be reset
integer :=16#055c# ADDR_REG_RO_IDELAYCTRL_RDY
this register reports the status of the io delay control circuits
std_logic_vector (2 downto 0) :="100" CONST_DPR_STATUS_WAIT_WRITE
integer :=16#164A# ADDR_REG_RO_MISSING_ET_RES_COUNTER
8 32-bit weighted/restricted missing ET threshold counters, 16 adresses, last one 1668 ...
integer :=16#12BC# ADDR_REG_RW_RTM_SPY_SYSTEMDS2_MEM_WORD
same for the ds 2 RTM spies
integer :=16#04DA# ADDR_REG_RO_INPUT_SPY_MEM_SOURCE_CHECK_ERROR
16 24-bit error latches last one is 16#0518#
integer :=16#12D4# ADDR_REG_RW_RTM_SPY_SOURCE_MEM_START_ADDRESS
integer :=16#12E0# ADDR_REG_RW_RTM_SPY_SYSTEMDS2_MEM_START_ADDRESS
std_logic_vector (3 downto 0) :="0010" CONST_DPR_CONTROL_PLAYBACK
integer :=16#5008# ADDR_REG_RO_VERSION_FLAVOR_LOCAL
integer :=16#1328# ADDR_REG_RO_RTM_OUTPUT_SPY_SYSTEM_MEM_STATUS
integer :=16#15A2# ADDR_REG_RO_TOTAL_OVERFLOW_COUNTER
32-bit total (backplane OR number of TOBs) overflow counter, 2 adresses
integer :=16#1394# ADDR_REG_RO_MULT_LOCAL_COUNTER
25 32-bit local rate counters (50 addresses), last one is 13F6
integer :=16#0464# ADDR_REG_RO_EV_COUNTER
32-bit event counter for the input module maxes out but doesn't overturn goes to 466 ...
integer :=16#1362# ADDR_REG_RO_CLOCK_DETECT_COUNTER
std_logic_vector (2 downto 0) :="010" CONST_DPR_STATUS_WAIT_INHIBIT
integer :=16#0576# ADDR_REG_RW_JET_THRESHOLD_BLOCK
integer :=16#11FE# ADDR_REG_RW_INPUT_SPY_MEM_SYSTEM_WORD
six consecutive addresses ending at 1208
integer :=16#051a# ADDR_REG_RO_INPUT_SPY_MEM_SOURCE_NOERROR_COUNTER
integer :=16#138C# ADDR_REG_RW_RATE_COUNTER_INHIBIT
bit 0 set stops the rate counters synchroneously
integer :=16#056A# ADDR_REG_RW_RX_POLARITY
integer :=16#129C# ADDR_REG_RW_CTP_SPY_MEM_CONTROL
control word word for the CTP spy memory
integer :=16#130A# ADDR_REG_RO_RTM_SPY_SYSTEM_MEM_CHECK_ERROR
integer :=16#1390# ADDR_REG_RO_RATE_NORMALISATION_COUNTER
32 bit rate normalisation counter (2 addresses)
integer :=16#159E# ADDR_REG_RO_GLOBAL_BACKPLANE_OVERFLOW_COUNTER
32-bit global backplane overflow counter, 2 addresses
integer :=16#1A4E# ADDR_REG_RW_SUM_ET_THR_BLOCK
8 15-bit SUM_ET THRESHOLDS, 8 address, last one 1A5C
integer :=16#155E# ADDR_REG_RO_LOCAL_BACKPLANE_OVERFLOW_COUNTER
16 32-bit local backplane overflow counters, last one is 159C
integer :=16#5004# ADDR_REG_RO_VERSION_FLAVOR_COMMON
integer :=16#131A# ADDR_REG_RW_BACKPLANE_INPUT_CHANNEL_MASK
integer :=16#15CA# ADDR_REG_RO_MISSING_ET_COUNTER
8 32-bit missing ET threshold counters, 16 adresses, last one 15E8
std_logic vme_wenia_vme,addr_vme,ncs,rd_nwr,
integer :=16#0564# ADDR_REG_RO_INPUT_MOD_COUNTER_ENABLE
counter enable values for the input module
1.8.6 
