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CMX
CMX firmware code in-line documentation
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CMX
CMX firmware code in-line documentation
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test registers More...
Package Body >> CMX_VME_defsFunctions | |
| std_logic | vme_ren ( ia_vme: in integer addr_vme: in std_logic_vector (15 downto 0) ncs: in std_logic rd_nwr: in std_logic ) |
| std_logic | vme_wen ( ia_vme: in integer addr_vme: in std_logic_vector (15 downto 0) ncs: in std_logic rd_nwr: in std_logic ) |
Libraries | |
| ieee | |
Use Clauses | |
| ieee.std_logic_1164.all | |
| ieee.numeric_std.all | |
Constants | |
| ADDR_REG_RO_test | integer := 16#0100# |
| test RO register | |
| ADDR_REG_RW_test | integer := 16#0102# |
| test RW register | |
| ADDR_REG_RO_backplane_forward | integer := 16#0104# |
| ADDR_REG_RW_IDELAY_BACKPLANE | integer := 16#0144# |
| 400 delay values last address is 16#0462# | |
| ADDR_REG_RO_EV_COUNTER | integer := 16#0464# |
| 32-bit event counter for the input module maxes out but doesn't overturn goes to 466 | |
| ADDR_REG_RO_PARITY_ERROR_COUNTER | integer := 16#0468# |
| ADDR_REG_RW_COUNTER_RESET | integer := 16#04A8# |
| counter reset - resets counters of events and errors | |
| ADDR_REG_RW_INPUT_SPY_MEM_SOURCE_WORD | integer := 16#04AA# |
| six consecutive addresses ending at 4B4 | |
| ADDR_REG_RW_INPUT_SPY_MEM_SOURCE_CONTROL | integer := 16#04B6# |
| control and status words with states defined below | |
| ADDR_REG_RO_INPUT_SPY_MEM_SOURCE_STATUS | integer := 16#04B8# |
| CONST_DPR_CONTROL_SPY | std_logic_vector ( 3 downto 0 ) := " 0001 " |
| CONST_DPR_CONTROL_PLAYBACK | std_logic_vector ( 3 downto 0 ) := " 0010 " |
| CONST_DPR_CONTROL_VERIFY | std_logic_vector ( 3 downto 0 ) := " 0011 " |
| CONST_DPR_STATUS_NORMAL | std_logic_vector ( 2 downto 0 ) := " 001 " |
| CONST_DPR_STATUS_WAIT_INHIBIT | std_logic_vector ( 2 downto 0 ) := " 010 " |
| CONST_DPR_STATUS_WAIT_READ | std_logic_vector ( 2 downto 0 ) := " 011 " |
| CONST_DPR_STATUS_WAIT_WRITE | std_logic_vector ( 2 downto 0 ) := " 100 " |
| CONST_DPR_STATUS_WRITE | std_logic_vector ( 2 downto 0 ) := " 101 " |
| CONST_DPR_STATUS_READ | std_logic_vector ( 2 downto 0 ) := " 110 " |
| ADDR_REG_RW_INPUT_SPY_MEM_SOURCE_START_ADDRESS | integer := 16#04BA# |
| 16 9-bit words (upper 7 bits unused), ending address 4D8 | |
| ADDR_REG_RO_INPUT_SPY_MEM_SOURCE_CHECK_ERROR | integer := 16#04DA# |
| 16 24-bit error latches last one is 16#0518# | |
| ADDR_REG_RO_INPUT_SPY_MEM_SOURCE_NOERROR_COUNTER | integer := 16#051a# |
| ADDR_REG_RW_CLOCK_MANAGER_RESET | integer := 16#055a# |
| ADDR_REG_RO_IDELAYCTRL_RDY | integer := 16#055c# |
| this register reports the status of the io delay control circuits | |
| ADDR_REG_RO_IDELAYCTRL_RST | integer := 16#055e# |
| current IDELAYCTRL reset status | |
| ADDR_REG_RO_IDELAYCTRL_WAS_RST | integer := 16#0560# |
| states if IDELAYCTRL has been reset | |
| ADDR_REG_RW_INPUT_MOD_RESET | integer := 16#0562# |
| async register for controlling the reset of the input module | |
| ADDR_REG_RO_INPUT_MOD_COUNTER_ENABLE | integer := 16#0564# |
| counter enable values for the input module | |
| ADDR_REG_RW_CTP_TESTER_DATA_SELECT | integer := 16#0566# |
| ADDR_REG_RW_TOPOTR_GTX_RESET | integer := 16#0568# |
| TOPO TR GTX RX (bit 0) TX (bit 1) reset. | |
| ADDR_REG_RW_RX_POLARITY | integer := 16#056A# |
| ADDR_REG_RW_TX_POLARITY | integer := 16#0570# |
| 3 consecutive addresses for the TX polarity | |
| ADDR_REG_RW_JET_THRESHOLD_BLOCK | integer := 16#0576# |
| ADDR_REG_RW_DAQ_SLICE | integer := 16#11F6# |
| ADDR_REG_RW_DAQ_RAM_OFFSET | integer := 16#11F8# |
| ADDR_REG_RW_BCID_RESET_VAL | integer := 16#11FA# |
| what is the value of the BCID we are get when the BC reset is received | |
| ADDR_REG_RW_DAQ_ROI_RESET | integer := 16#11FC# |
| the LSB of this will cause the DAQ machinery to be reset | |
| ADDR_REG_RW_INPUT_SPY_MEM_SYSTEM_WORD | integer := 16#11FE# |
| six consecutive addresses ending at 1208 | |
| ADDR_REG_RW_INPUT_SPY_MEM_SYSTEM_CONTROL | integer := 16#120A# |
| control and status words with states defined below | |
| ADDR_REG_RO_INPUT_SPY_MEM_SYSTEM_STATUS | integer := 16#120C# |
| ADDR_REG_RW_INPUT_SPY_MEM_SYSTEM_START_ADDRESS | integer := 16#120E# |
| one 8-bit words (upper 8 bits unused) | |
| ADDR_REG_RO_INPUT_SPY_MEM_SYSTEM_CHECK_ERROR | integer := 16#1210# |
| ADDR_REG_RO_INPUT_SPY_MEM_SYSTEM_NOERROR_COUNTER | integer := 16#1250# |
| ADDR_REG_RW_SPY_MEM_WRITE_INHIBIT | integer := 16#1290# |
| ADDR_REG_RW_CTP_OUTPUT_COUNTER_RESET | integer := 16#1292# |
| ADDR_REG_RW_CTP_SPY_MEM_WORD | integer := 16#1294# |
| ADDR_REG_RW_CTP_SPY_MEM_CONTROL | integer := 16#129C# |
| control word word for the CTP spy memory | |
| ADDR_REG_RO_CTP_SPY_MEM_STATUS | integer := 16#129E# |
| status word for the CTP spy memory | |
| ADDR_REG_RW_CTP_SPY_MEM_START_ADDRESS | integer := 16#12A0# |
| start address for the CTP Spy memory | |
| ADDR_REG_RO_CTP_SPY_MEM_CHECK_ERROR | integer := 16#12A2# |
| ADDR_REG_RO_CTP_SPY_MEM_NOERROR_COUNTER | integer := 16#12AA# |
| ADDR_REG_RW_RTM_INPUT_COUNTER_RESET | integer := 16#12AE# |
| reset for the RTM input module counters | |
| ADDR_REG_RW_RTM_SPY_SOURCE_MEM_WORD | integer := 16#12B0# |
| ADDR_REG_RW_RTM_SPY_SOURCE_MEM_CONTROL | integer := 16#12B8# |
| control | |
| ADDR_REG_RO_RTM_SPY_SOURCE_MEM_STATUS | integer := 16#12BA# |
| status | |
| ADDR_REG_RW_RTM_SPY_SYSTEMDS2_MEM_WORD | integer := 16#12BC# |
| same for the ds 2 RTM spies | |
| ADDR_REG_RW_RTM_SPY_SYSTEMDS2_MEM_CONTROL | integer := 16#12C4# |
| ADDR_REG_RO_RTM_SPY_SYSTEMDS2_MEM_STATUS | integer := 16#12C6# |
| ADDR_REG_RW_RTM_SPY_SYSTEM_MEM_WORD | integer := 16#12C8# |
| same for the system RTM spies | |
| ADDR_REG_RW_RTM_SPY_SYSTEM_MEM_CONTROL | integer := 16#12D0# |
| ADDR_REG_RO_RTM_SPY_SYSTEM_MEM_STATUS | integer := 16#12D2# |
| ADDR_REG_RW_RTM_SPY_SOURCE_MEM_START_ADDRESS | integer := 16#12D4# |
| ADDR_REG_RW_RTM_SPY_SYSTEM_MEM_START_ADDRESS | integer := 16#12DA# |
| one register each for the start adresses for the system and ds2 rams | |
| ADDR_REG_RW_RTM_SPY_SYSTEMDS2_MEM_START_ADDRESS | integer := 16#12E0# |
| ADDR_REG_RO_RTM_PARITY_ERROR_COUNTER | integer := 16#12E6# |
| ADDR_REG_RO_RTM_SPY_SOURCE_MEM_CHECK_ERROR | integer := 16#12F2# |
| ADDR_REG_RO_RTM_SPY_SYSTEMDS2_MEM_CHECK_ERROR | integer := 16#12FE# |
| ADDR_REG_RO_RTM_SPY_SYSTEM_MEM_CHECK_ERROR | integer := 16#130A# |
| ADDR_REG_RO_CLOCK_MANAGER_STATUS | integer := 16#1316# |
| PLL status (bit 0 is DS1 MMCM lock and bit 1 is for DS2 MMCM) | |
| ADDR_REG_RW_DELAY_INPUT_DATA_ADDER | integer := 16#1318# |
| Delay for the input adder data. | |
| ADDR_REG_RW_BACKPLANE_INPUT_CHANNEL_MASK | integer := 16#131A# |
| ADDR_REG_RW_RTM_OUTPUT_COUNTER_RESET | integer := 16#131C# |
| error counter reset register for the RTM output module | |
| ADDR_REG_RW_RTM_OUTPUT_SPY_SYSTEM_MEM_WORD | integer := 16#131E# |
| ADDR_REG_RW_RTM_OUTPUT_SPY_SYSTEM_MEM_CONTROL | integer := 16#1326# |
| output RTM spy control and status | |
| ADDR_REG_RO_RTM_OUTPUT_SPY_SYSTEM_MEM_STATUS | integer := 16#1328# |
| ADDR_REG_RO_RTM_OUTPUT_SPY_SYSTEM_MEM_CHECK_ERROR | integer := 16#132A# |
| ADDR_REG_RW_RTM_OUTPUT_SPY_SYSTEM_MEM_START_ADDRESS | integer := 16#1336# |
| start address for the RTM spy memory | |
| ADDR_REG_RW_DAQ_RAM_RELATIVE_OFFSET | integer := 16#1338# |
| ADDR_REG_RW_SUMET_MASK | integer := 16#135E# |
| mask for the restricted range sum ET | |
| ADDR_REG_RW_MISSET_MASK | integer := 16#1360# |
| mask for the restricted range missing ET | |
| ADDR_REG_RO_CLOCK_DETECT_COUNTER | integer := 16#1362# |
| ADDR_REG_RW_QUIET_FORCE | integer := 16#1382# |
| ADDR_REG_RW_RTM_INPUT_CHANNEL_MASK | integer := 16#1384# |
| mask for the RTM inputs. | |
| ADDR_REG_RO_DAQ_ROI_STATUS | integer := 16#1386# |
| ADDR_REG_RW_DAQ_ROI_GTX_RESET | integer := 16#1388# |
| bit 0 reset DAQ, bit 1 resets ROI GTX (should be done at the same time) | |
| ADDR_REG_RO_TOPOTR_GTX_STATUS | integer := 16#138A# |
| bit 0 gives status of RX; bit 1 gives status of TX | |
| ADDR_REG_RW_RATE_COUNTER_INHIBIT | integer := 16#138C# |
| bit 0 set stops the rate counters synchroneously | |
| ADDR_REG_RW_RATE_COUNTER_RESET | integer := 16#138E# |
| bit 0 set resets (and holds reset) the rate counters | |
| ADDR_REG_RO_RATE_NORMALISATION_COUNTER | integer := 16#1390# |
| 32 bit rate normalisation counter (2 addresses) | |
| ADDR_REG_RO_MULT_LOCAL_COUNTER | integer := 16#1394# |
| 25 32-bit local rate counters (50 addresses), last one is 13F6 | |
| ADDR_REG_RO_MULT_REMOTE_COUNTER | integer := 16#13F8# |
| ADDR_REG_RO_MULT_TOTAL_COUNTER | integer := 16#14BA# |
| 25 32-bit global rate counters (50 addresses), last one is 151C | |
| ADDR_REG_RO_TOB_COUNTER | integer := 16#151E# |
| 16 32-bit tob counters (32 adresses), last one is 155C | |
| ADDR_REG_RO_LOCAL_BACKPLANE_OVERFLOW_COUNTER | integer := 16#155E# |
| 16 32-bit local backplane overflow counters, last one is 159C | |
| ADDR_REG_RO_GLOBAL_BACKPLANE_OVERFLOW_COUNTER | integer := 16#159E# |
| 32-bit global backplane overflow counter, 2 addresses | |
| ADDR_REG_RO_TOTAL_OVERFLOW_COUNTER | integer := 16#15A2# |
| 32-bit total (backplane OR number of TOBs) overflow counter, 2 adresses | |
| ADDR_REG_RO_BC_RESET_ERROR_COUNTER | integer := 16#15A6# |
| ADDR_REG_RW_BC_RESET_ERROR_COUNTER_RESET | integer := 16#15A8# |
| hold bit 0 high to reset the BCRESET error counter | |
| ADDR_REG_RO_SUM_ET_COUNTER | integer := 16#15AA# |
| 8 32-bit sum ET threshold counters, 16 adresses, last one 15C8 | |
| ADDR_REG_RO_MISSING_ET_COUNTER | integer := 16#15CA# |
| 8 32-bit missing ET threshold counters, 16 adresses, last one 15E8 | |
| ADDR_REG_RO_MISSING_ET_SIGN_COUNTER | integer := 16#160A# |
| 8 32-bit missing ET significance threshold counters, 16 adresses, last one 1628 | |
| ADDR_REG_RO_SUM_ET_WEIGHTED_COUNTER | integer := 16#162A# |
| 8 32-bit weighted/restricted sum ET threshold counters, 16 adresses, last one 1648 | |
| ADDR_REG_RO_MISSING_ET_RES_COUNTER | integer := 16#164A# |
| 8 32-bit weighted/restricted missing ET threshold counters, 16 adresses, last one 1668 | |
| ADDR_REG_RO_PRESENCE_COUNTER | integer := 16#166A# |
| 224 32-bit counters, 448 addresses, last one is 19EA | |
| ADDR_REG_RW_DISABLE_OVERFLOW_MASK | integer := 16#19EC# |
| ADDR_REG_RO_SYSMON_DATA_BLOCK | integer := 16#19EE# |
| reserve 16 addresses for the sysmon, in first implementation 15 are used | |
| ADDR_REG_RW_MISS_E_THR_BLOCK | integer := 16#1A0E# |
| 8 31-bit MISS_E THRESHOLDS, 16 address, last one 1A2C | |
| ADDR_REG_RW_MISS_E_RES_THR_BLOCK | integer := 16#1A2E# |
| 8 31-bit MISS_E_RES THRESHOLDS, 16 address, last one 1A4C | |
| ADDR_REG_RW_SUM_ET_THR_BLOCK | integer := 16#1A4E# |
| 8 15-bit SUM_ET THRESHOLDS, 8 address, last one 1A5C | |
| ADDR_REG_RW_SUM_ET_RES_THR_BLOCK | integer := 16#1A5E# |
| 8 15-bit SUM_ET_RES THRESHOLDS, 8 address, last one 1A6C | |
| ADDR_REG_RW_XS_T2_A2_THR_BLOCK | integer := 16#1A6E# |
| 8 31-bit XS_T2_A2 THRESHOLDS, 16 address, last one 1A8C | |
| ADDR_REG_RW_T_MISS_E_MIN_PARAM_BLOCK | integer := 16#1A8E# |
| 8 31-bit T_MISS_E_MIN PARAM, 16 address, last one 1AAC | |
| ADDR_REG_RW_T_MISS_E_MAX_PARAM_BLOCK | integer := 16#1AAE# |
| 8 31-bit T_MISS_E_MAX PARAM, 16 address, last one 1ACC | |
| ADDR_REG_RW_T_SUM_E_MIN_PARAM_BLOCK | integer := 16#1ACE# |
| 8 15-bit T_SUM_E_MIN PARAM, 8 address, last one 1ADC | |
| ADDR_REG_RW_T_SUM_E_MAX_PARAM_BLOCK | integer := 16#1ADE# |
| 8 15-bit T_SUM_E_MAX PARAM, 8 address, last one 1AEC | |
| ADDR_REG_RW_XS_B2_PARAM_BLOCK | integer := 16#1AEE# |
| 8 15-bit XS_B PARAM, 8 address last one 1AFC | |
| ADDR_REG_RO_CLOCK_DIFF_DETECT_COUNTER | integer := 16#1AFE# |
| ADDR_REG_RO_CLOCK_DIFF_DURATION_COUNTER | integer := 16#1B3E# |
| ADDR_REG_RO_CLOCK_DIFF_RATCHET_UP_COUNTER | integer := 16#1B7E# |
| ADDR_REG_RO_CLOCK_DIFF_RATCHET_DOWN_COUNTER | integer := 16#1BBE# |
| ADDR_REG_RO_CMX_FLAVOR | integer := 16#4998# |
| ADDR_REG_RO_VERSION_COMMON | integer := 16#5000# |
| version registers | |
| ADDR_REG_RO_VERSION_FLAVOR_COMMON | integer := 16#5004# |
| ADDR_REG_RO_VERSION_FLAVOR_LOCAL | integer := 16#5008# |
test registers
Definition at line 13 of file CMX_VME_defs.vhd.
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Function |
Definition at line 434 of file CMX_VME_defs.vhd.
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Function |
Definition at line 443 of file CMX_VME_defs.vhd.
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Constant |
beginning fo the 32 addresses for forwarding the backplane data for test purpose only.
Definition at line 22 of file CMX_VME_defs.vhd.
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Constant |
16-bit counter of BCID errors counter is incremented when upon the reception of bc reset the counter is not at the expected value
Definition at line 329 of file CMX_VME_defs.vhd.
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Constant |
clock detect counters 16 adresses, last one is 1380
Definition at line 264 of file CMX_VME_defs.vhd.
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Constant |
16 32 bit clock difference counters for each backplane input the counter counts the difference between the system clock ticks and (/2) forwarded clock ticks the clock reset (REG_RW_COUNTER_RESET) must be used periodically, otherwise the counters will top-out and the diference will be 0 irrespective of the clock behavior last one is 1B3C
Definition at line 397 of file CMX_VME_defs.vhd.
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Constant |
16 32 bit clock difference duration counters every cycle that the system clock is different from the backplane (/2) clock the counter is incremented last one is 1B7C
Definition at line 404 of file CMX_VME_defs.vhd.
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Constant |
same as above but ratched down last one is 1BFC
Definition at line 414 of file CMX_VME_defs.vhd.
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Constant |
ratchet up difference counters every cycle a check is made if the CLOCK_DIFF_DETECT_COUNTER is higher then previous maximum and if yes the maximum is incremented last one is 1BBC
Definition at line 410 of file CMX_VME_defs.vhd.
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Constant |
PLL status (bit 0 is DS1 MMCM lock and bit 1 is for DS2 MMCM)
Definition at line 223 of file CMX_VME_defs.vhd.
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Constant |
cmx flavor number value of the register corresponds to the 'revision' number on the CF (using v5.4 of the BSPT FW): 2=EM/TAU Crate; 3=EM/TAU System; 4=SumET Crate; 5=SumET System; 6=Jet Crate; 7=Jet System 0,1 are 'special'
Definition at line 425 of file CMX_VME_defs.vhd.
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Constant |
error latches for the CTP Spy memory there are 4 addresses last one is 16#12A8#
Definition at line 167 of file CMX_VME_defs.vhd.
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Constant |
32-bit no error counter for the CTP spy two addresses here!!!
Definition at line 172 of file CMX_VME_defs.vhd.
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Constant |
status word for the CTP spy memory
Definition at line 159 of file CMX_VME_defs.vhd.
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Constant |
status of the GTX's driving the DAQ and ROI SFPs meaning of bits: 0: local_pll_lock_out_SFP_DAQ 1: GTX_TX_READY_OUT_TX_SFP_DAQ 2: GTX_RX_READY_OUT_TX_SFP_DAQ 3: PLLLKDET_diag_TX_SFP_DAQ 4: local_pll_lock_out_SFP_ROI 5: GTX_TX_READY_OUT_TX_SFP_ROI 6: GTX_RX_READY_OUT_TX_SFP_ROI 7: PLLLKDET_diag_TX_SFP_ROI 8: readout_rst_out
Definition at line 287 of file CMX_VME_defs.vhd.
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Constant |
32-bit event counter for the input module maxes out but doesn't overturn goes to 466
Definition at line 29 of file CMX_VME_defs.vhd.
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Constant |
32-bit global backplane overflow counter, 2 addresses
Definition at line 321 of file CMX_VME_defs.vhd.
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Constant |
this register reports the status of the io delay control circuits
Definition at line 73 of file CMX_VME_defs.vhd.
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Constant |
current IDELAYCTRL reset status
Definition at line 76 of file CMX_VME_defs.vhd.
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Constant |
states if IDELAYCTRL has been reset
Definition at line 79 of file CMX_VME_defs.vhd.
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Constant |
counter enable values for the input module
Definition at line 85 of file CMX_VME_defs.vhd.
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Constant |
16 24-bit error latches last one is 16#0518#
Definition at line 62 of file CMX_VME_defs.vhd.
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Constant |
16 32-bit counters that stop when a first bit error on any bit is encountered last address is 16#0558#
Definition at line 66 of file CMX_VME_defs.vhd.
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Constant |
Definition at line 45 of file CMX_VME_defs.vhd.
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Constant |
16 24-bit error latches last one is 16## last address is 124E
Definition at line 135 of file CMX_VME_defs.vhd.
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Constant |
16 32-bit counters that stop when a first bit error on any bit on any channel is encountered last address is 128E
Definition at line 140 of file CMX_VME_defs.vhd.
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Constant |
Definition at line 128 of file CMX_VME_defs.vhd.
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Constant |
16 32-bit local backplane overflow counters, last one is 159C
Definition at line 318 of file CMX_VME_defs.vhd.
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Constant |
8 32-bit missing ET threshold counters, 16 adresses, last one 15E8
Definition at line 338 of file CMX_VME_defs.vhd.
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Constant |
8 32-bit weighted/restricted missing ET threshold counters, 16 adresses, last one 1668
Definition at line 347 of file CMX_VME_defs.vhd.
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Constant |
8 32-bit missing ET significance threshold counters, 16 adresses, last one 1628
Definition at line 341 of file CMX_VME_defs.vhd.
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Constant |
25 32-bit local rate counters (50 addresses), last one is 13F6
Definition at line 305 of file CMX_VME_defs.vhd.
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Constant |
25 32-bit remote rate counters (96 addresses), last one is 14B8 96 addresses because CP has 16 thresholds x3 cables x2 words/counter
Definition at line 309 of file CMX_VME_defs.vhd.
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Constant |
25 32-bit global rate counters (50 addresses), last one is 151C
Definition at line 312 of file CMX_VME_defs.vhd.
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Constant |
16 32-bit parity error counters for the input module these also max out but don't overturn last address is 4A6
Definition at line 34 of file CMX_VME_defs.vhd.
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Constant |
224 32-bit counters, 448 addresses, last one is 19EA
Definition at line 350 of file CMX_VME_defs.vhd.
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Constant |
32 bit rate normalisation counter (2 addresses)
Definition at line 302 of file CMX_VME_defs.vhd.
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Constant |
bit error latch; six addresses (two per cable x max 3 cables) last one is 16#1334#
Definition at line 246 of file CMX_VME_defs.vhd.
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Constant |
Definition at line 241 of file CMX_VME_defs.vhd.
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Constant |
parity error counters each counter is 32bits (so 2 addresses) and there are max three counters (there may be 3 rtm cables coming in) so reserve six addresses total. last one is 12F0
Definition at line 206 of file CMX_VME_defs.vhd.
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Constant |
bit error latches for RTM source 2 bytes per latch and possibly 3 cables so six addresses total last one is 12fc
Definition at line 212 of file CMX_VME_defs.vhd.
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Constant |
status
Definition at line 183 of file CMX_VME_defs.vhd.
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Constant |
same for system last one is 1314
Definition at line 220 of file CMX_VME_defs.vhd.
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Constant |
Definition at line 193 of file CMX_VME_defs.vhd.
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Constant |
same for ds2 last one is 1308
Definition at line 216 of file CMX_VME_defs.vhd.
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Constant |
Definition at line 188 of file CMX_VME_defs.vhd.
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Constant |
8 32-bit sum ET threshold counters, 16 adresses, last one 15C8
Definition at line 335 of file CMX_VME_defs.vhd.
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Constant |
8 32-bit weighted/restricted sum ET threshold counters, 16 adresses, last one 1648
Definition at line 344 of file CMX_VME_defs.vhd.
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Constant |
reserve 16 addresses for the sysmon, in first implementation 15 are used
Definition at line 357 of file CMX_VME_defs.vhd.
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Constant |
test RO register
Definition at line 17 of file CMX_VME_defs.vhd.
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Constant |
16 32-bit tob counters (32 adresses), last one is 155C
Definition at line 315 of file CMX_VME_defs.vhd.
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Constant |
bit 0 gives status of RX; bit 1 gives status of TX
Definition at line 293 of file CMX_VME_defs.vhd.
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Constant |
32-bit total (backplane OR number of TOBs) overflow counter, 2 adresses
Definition at line 324 of file CMX_VME_defs.vhd.
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Constant |
version registers
Definition at line 428 of file CMX_VME_defs.vhd.
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Constant |
Definition at line 429 of file CMX_VME_defs.vhd.
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Constant |
Definition at line 430 of file CMX_VME_defs.vhd.
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Constant |
channel mask bit q set to '1' will zero out data from input q parity will be set to 1 in the data presented to downstream logic
Definition at line 230 of file CMX_VME_defs.vhd.
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Constant |
hold bit 0 high to reset the BCRESET error counter
Definition at line 332 of file CMX_VME_defs.vhd.
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Constant |
what is the value of the BCID we are get when the BC reset is received
Definition at line 117 of file CMX_VME_defs.vhd.
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Constant |
system MMCM reset register; writing '1' to LS bit causes MMCM to be held in reset state (so write a '0' right after)
Definition at line 70 of file CMX_VME_defs.vhd.
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Constant |
counter reset - resets counters of events and errors
Definition at line 37 of file CMX_VME_defs.vhd.
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Constant |
a write to this address will reset the error counters and latches in the CTP output module
Definition at line 149 of file CMX_VME_defs.vhd.
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Constant |
control word word for the CTP spy memory
Definition at line 156 of file CMX_VME_defs.vhd.
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Constant |
start address for the CTP Spy memory
Definition at line 162 of file CMX_VME_defs.vhd.
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Constant |
CTP Spy memory data access four addresses starting at this one; last one is 16#129A#
Definition at line 153 of file CMX_VME_defs.vhd.
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Constant |
CTP tester data source select LSB=0 means pre-defined pattern LSB=1 pseudo-random
Definition at line 89 of file CMX_VME_defs.vhd.
|
Constant |
how far back in the buffer memory we need to look to find the event that has caused the L1A we are currently getting
Definition at line 114 of file CMX_VME_defs.vhd.
|
Constant |
beginning adresses for the relative DAQ offsets (19 addresses) last one is 16#135C#
Definition at line 254 of file CMX_VME_defs.vhd.
|
Constant |
bit 0 reset DAQ, bit 1 resets ROI GTX (should be done at the same time)
Definition at line 290 of file CMX_VME_defs.vhd.
|
Constant |
the LSB of this will cause the DAQ machinery to be reset
Definition at line 120 of file CMX_VME_defs.vhd.
|
Constant |
define how many "slices" to read out with the event causing the L1A being the middle "slice" only two LSB are used 00: one slice; 01: three slices; 10: five slices
Definition at line 110 of file CMX_VME_defs.vhd.
|
Constant |
Delay for the input adder data.
Definition at line 226 of file CMX_VME_defs.vhd.
|
Constant |
mask for overflow behavior, set any of bits (1-14(CP),0-15(JET)) to disable trigger force on overflow discovery from corresponding source module
Definition at line 354 of file CMX_VME_defs.vhd.
|
Constant |
400 delay values last address is 16#0462#
Definition at line 25 of file CMX_VME_defs.vhd.
|
Constant |
async register for controlling the reset of the input module
Definition at line 82 of file CMX_VME_defs.vhd.
|
Constant |
control and status words with states defined below
Definition at line 44 of file CMX_VME_defs.vhd.
|
Constant |
16 9-bit words (upper 7 bits unused), ending address 4D8
Definition at line 59 of file CMX_VME_defs.vhd.
|
Constant |
six consecutive addresses ending at 4B4
Definition at line 41 of file CMX_VME_defs.vhd.
|
Constant |
control and status words with states defined below
Definition at line 127 of file CMX_VME_defs.vhd.
|
Constant |
one 8-bit words (upper 8 bits unused)
Definition at line 131 of file CMX_VME_defs.vhd.
|
Constant |
six consecutive addresses ending at 1208
Definition at line 124 of file CMX_VME_defs.vhd.
|
Constant |
CMX Jet threshold definition 16#0576# 16#11f4# 25 THR x 16 JEMs x 2 eta local positions x 2 fine positions = 1600 registers (x2 for addressing).
Definition at line 104 of file CMX_VME_defs.vhd.
|
Constant |
8 31-bit MISS_E_RES THRESHOLDS, 16 address, last one 1A4C
Definition at line 364 of file CMX_VME_defs.vhd.
|
Constant |
8 31-bit MISS_E THRESHOLDS, 16 address, last one 1A2C
Definition at line 361 of file CMX_VME_defs.vhd.
|
Constant |
mask for the restricted range missing ET
Definition at line 260 of file CMX_VME_defs.vhd.
|
Constant |
control for quiet/force accept behavior bit 0 set will cause a force accept in case of a parity error on the backplane or on an RTM cable bit 1 set will cause data from problematic input module/cable to be zeroed
Definition at line 270 of file CMX_VME_defs.vhd.
|
Constant |
bit 0 set stops the rate counters synchroneously
Definition at line 296 of file CMX_VME_defs.vhd.
|
Constant |
bit 0 set resets (and holds reset) the rate counters
Definition at line 299 of file CMX_VME_defs.vhd.
|
Constant |
mask for the RTM inputs.
Definition at line 274 of file CMX_VME_defs.vhd.
|
Constant |
reset for the RTM input module counters
Definition at line 175 of file CMX_VME_defs.vhd.
|
Constant |
error counter reset register for the RTM output module
Definition at line 233 of file CMX_VME_defs.vhd.
|
Constant |
output RTM spy control and status
Definition at line 240 of file CMX_VME_defs.vhd.
|
Constant |
start address for the RTM spy memory
Definition at line 249 of file CMX_VME_defs.vhd.
|
Constant |
4 addresses for the RTM output spy words last one is 16#1324#
Definition at line 237 of file CMX_VME_defs.vhd.
|
Constant |
control
Definition at line 181 of file CMX_VME_defs.vhd.
|
Constant |
max three addresses for the start pointers (since there are max 3 input rtm cables) for the source memory
Definition at line 197 of file CMX_VME_defs.vhd.
|
Constant |
data words for the RTM 'SOURCE' SPY memory 4 words; last address 12b6
Definition at line 179 of file CMX_VME_defs.vhd.
|
Constant |
Definition at line 192 of file CMX_VME_defs.vhd.
|
Constant |
one register each for the start adresses for the system and ds2 rams
Definition at line 199 of file CMX_VME_defs.vhd.
|
Constant |
same for the system RTM spies
Definition at line 191 of file CMX_VME_defs.vhd.
|
Constant |
Definition at line 187 of file CMX_VME_defs.vhd.
|
Constant |
Definition at line 200 of file CMX_VME_defs.vhd.
|
Constant |
same for the ds 2 RTM spies
Definition at line 186 of file CMX_VME_defs.vhd.
|
Constant |
3 consecutive addresses for the RX polarity (RX is not used on Base function but the functionality in FW is provided
Definition at line 96 of file CMX_VME_defs.vhd.
|
Constant |
writing 1 to LSB triggers a synchroneous lock on writing to the spy memories this is to for reading out different memories as a snapshot of activity from entire CMX
Definition at line 145 of file CMX_VME_defs.vhd.
|
Constant |
8 15-bit SUM_ET_RES THRESHOLDS, 8 address, last one 1A6C
Definition at line 370 of file CMX_VME_defs.vhd.
|
Constant |
8 15-bit SUM_ET THRESHOLDS, 8 address, last one 1A5C
Definition at line 367 of file CMX_VME_defs.vhd.
|
Constant |
mask for the restricted range sum ET
Definition at line 257 of file CMX_VME_defs.vhd.
|
Constant |
8 31-bit T_MISS_E_MAX PARAM, 16 address, last one 1ACC
Definition at line 379 of file CMX_VME_defs.vhd.
|
Constant |
8 31-bit T_MISS_E_MIN PARAM, 16 address, last one 1AAC
Definition at line 376 of file CMX_VME_defs.vhd.
|
Constant |
8 15-bit T_SUM_E_MAX PARAM, 8 address, last one 1AEC
Definition at line 385 of file CMX_VME_defs.vhd.
|
Constant |
8 15-bit T_SUM_E_MIN PARAM, 8 address, last one 1ADC
Definition at line 382 of file CMX_VME_defs.vhd.
|
Constant |
test RW register
Definition at line 18 of file CMX_VME_defs.vhd.
|
Constant |
TOPO TR GTX RX (bit 0) TX (bit 1) reset.
Definition at line 92 of file CMX_VME_defs.vhd.
|
Constant |
3 consecutive addresses for the TX polarity
Definition at line 99 of file CMX_VME_defs.vhd.
|
Constant |
8 15-bit XS_B PARAM, 8 address last one 1AFC
Definition at line 388 of file CMX_VME_defs.vhd.
|
Constant |
8 31-bit XS_T2_A2 THRESHOLDS, 16 address, last one 1A8C
Definition at line 373 of file CMX_VME_defs.vhd.
|
Constant |
Definition at line 48 of file CMX_VME_defs.vhd.
|
Constant |
Definition at line 47 of file CMX_VME_defs.vhd.
|
Constant |
Definition at line 49 of file CMX_VME_defs.vhd.
|
Constant |
Definition at line 51 of file CMX_VME_defs.vhd.
|
Constant |
Definition at line 56 of file CMX_VME_defs.vhd.
|
Constant |
Definition at line 52 of file CMX_VME_defs.vhd.
|
Constant |
Definition at line 53 of file CMX_VME_defs.vhd.
|
Constant |
Definition at line 54 of file CMX_VME_defs.vhd.
|
Constant |
Definition at line 55 of file CMX_VME_defs.vhd.
|
Library |
Definition at line 8 of file CMX_VME_defs.vhd.
|
Package |
Definition at line 10 of file CMX_VME_defs.vhd.
|
Package |
Definition at line 9 of file CMX_VME_defs.vhd.
1.8.6 
