cmm_board_select_rtl.vhd

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--
-- VHDL Architecture CMM_VME_Interface_v2_3.CMM_Board_Select.rtl
--
-- Created:
--          by - ipb28.UNKNOWN (TE2BELARUS)
--          at - 16:27:16 13/10/2005
--
-- using Mentor Graphics HDL Designer(TM) 2005.1 (Build 83)
--
-- The VME-- base address ranges:
-- CrateSlotNumber Module VME-- address
-- 3               CMM0   0x00700000-0x0077FFFE : VME address (23 DOWNTO 1): 0x700000 -> "0111_0000_0000_0000_0000_000x"
-- 20              CMM1   0x00780000-0x007FFFFE : VME address (23 DOWNTO 1): 0x780000 -> "0111_1000_0000_0000_0000_000x"
-- GEOADD(0) - 0 (Left) 1 (Right)

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;

entity CMM_Board_Select is
    port( 
        addressbus     : in     std_logic_vector (23 downto 19);
        geoaddr_0      : in     std_logic;
        board_select_n : out    std_logic
    );
end CMM_Board_Select ;

--------------------------------------------------------------------------------
architecture rtl of cmm_board_select is
--------------------------------------------------------------------------------
-- IPB 2005, from a flow chart by Panagiotis.
--------------------------------------------------------------------------------
begin
  
  allproc: process (addressbus, geoaddr_0) 
  begin
   if (addressbus(23 downto 20)="0111") and (addressbus(19)= geoaddr_0) then
      board_select_n <= '0';
    else
      board_select_n <= '1';    
    end if;
  end process;    
    
end architecture rtl;