BUF_2X24_AT_80_TO_1X96_AT_40.vhd

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

library work;
use work.CMXpackage.all;


-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity BUF_2X24_AT_80_TO_1X96_AT_40 is
  port (
    PDATA, NDATA : in  std_logic_vector(numbitsinchan - 1 downto 0);
    ODATA        : out std_logic_vector((numbitsinchan*4)-1 downto 0);
    ODATA_first_half : out std_logic_vector((numbitsinchan*2)-1 downto 0);
    clk80 : in std_logic;
    cyclecounter :  in unsigned(0 downto 0);
    counter_enable : in std_logic;
    PAR_ERROR    : out std_logic);
end BUF_2X24_AT_80_TO_1X96_AT_40;

architecture Behavioral of BUF_2X24_AT_80_TO_1X96_AT_40 is

  attribute keep : string;  

  signal PDATA_24, NDATA_24: std_logic_vector(23 downto 0);

  
  
  signal P_temp_reg : std_logic_vector(numbitsinchan -1 downto 0);  -- holds
                                                                    -- first
                                                                    -- part of
                                                                    -- PDATA
                                                                    -- for
                                                                    -- half
                                                                    -- cycle
                                                                    -- of
                                                                    -- 40MHz
                                                                    -- Clock
  
  signal N_temp_reg : std_logic_vector(numbitsinchan -1 downto 0);  --same for
                                                                    --NDATA
  
  --signal P_temp_reg1,N_temp_reg1 : std_logic_vector(numbitsinchan -1 downto 0);
  
  signal parP, parN : std_logic;        -- holds the parity for
                                        -- the P and N line

  signal parP_odd_err, parN_odd_err : std_logic; --'1' if we did not get odd
                                                 --parity data
  
  signal parP_odd_err_reg, parN_odd_err_reg : std_logic; --hold parity error for the first
                                         --1 set of 24 bits (rising 40MHz
                                         --clock edge)

  -- -- signal PDATA_msb0, NDATA_msb0 : std_logic_vector(numbitsinchan-1 downto 0);  
  -- --   --PDATA_reg_msb0, NDATA_reg_msb0 : std_logic_vector(numbitsinchan-1 downto 0);  
  -- --                                       -- corresponding signals
  -- --                                       -- with the msb set to 0
  -- --                                       -- for parity calculation

  --attribute keep of P_temp_reg1, N_temp_reg1,
  attribute keep of parP_odd_err, parN_odd_err, parP_odd_err_reg, parN_odd_err_reg : signal is "TRUE";
    
  component PARITY_CALC
    port (
      DATA   : in  std_logic_vector(numbitsinchan - 1 downto 0);
      PARITY : out std_logic);
  end component;
  
begin

  --PDATA_24(23 downto (23-(numbitsinchan-1))) <= PDATA;
  --NDATA_24(23 downto (23-(numbitsinchan-1))) <= NDATA;
  --genZEROS: if numbitsinchan<24 generate
  --  PDATA_24(23-(numbitsinchan-1)-1 downto 0) <= (others=>'0');
  --  NDATA_24(23-(numbitsinchan-1)-1 downto 0) <= (others=>'0');
  --end generate genZEROS;

  --- ---PDATA_msb0(numbitsinchan-2 downto 0)<=PDATA(numbitsinchan-2 downto 0);
  --- ---PDATA_msb0(numbitsinchan-1)<='0';
  --- ---NDATA_msb0(numbitsinchan-2 downto 0)<=NDATA(numbitsinchan-2 downto 0);
  --- ---NDATA_msb0(numbitsinchan-1)<='0';

  --PDATA_reg_msb0(numbitsinchan-2 downto 0)<=PDATA_reg(numbitsinchan-2 downto 0);
  --PDATA_reg_msb0(numbitsinchan-1)<='0';
  --NDATA_reg_msb0(numbitsinchan-2 downto 0)<=NDATA_reg(numbitsinchan-2 downto 0);
  --NDATA_reg_msb0(numbitsinchan-1)<='0';

  
  
  
  
  pcalcP: PARITY_CALC port map (PDATA, parP);
  pcalcN: PARITY_CALC port map (NDATA, parN);          
  
  parP_odd_err<=parP xor '1';  --these will be '1' if the parity result is '0'
  parN_odd_err<=parN xor '1';  --i.e. the received data had even parity (we
                               --expect odd)
  
  process(clk80)
  begin
    if rising_edge(clk80) then
      if counter_enable='0' then
        ODATA<=(others=>'0');
        ODATA_first_half<=(others=>'0');
        P_temp_reg<=(others=>'0');
        N_temp_reg<=(others=>'0');
        parP_odd_err_reg<='0';
        parN_odd_err_reg<='0';
        PAR_ERROR<='0';
      else
        
        if cyclecounter=to_unsigned(0,1) then
          P_temp_reg <= PDATA;
          N_temp_reg <= NDATA;
          parP_odd_err_reg<=parP_odd_err;
          parN_odd_err_reg<=parN_odd_err;
          ODATA_first_half(numbitsinchan-1 downto 0)<=PDATA;
          ODATA_first_half(2*numbitsinchan-1 downto numbitsinchan)<=NDATA;
        else
          --P_temp_reg1<=PDATA;
          --N_temp_reg1<=NDATA;

          -- reversed order --ODATA( (4*numbitsinchan-1) downto (3*numbitsinchan)) <= P_temp_reg;
          -- reversed order --ODATA( (3*numbitsinchan)-1 downto (2*numbitsinchan)) <= N_temp_reg;
          -- reversed order --ODATA( (2*numbitsinchan)-1 downto (1*numbitsinchan)) <=PDATA;
          -- reversed order --ODATA( (1*numbitsinchan)-1 downto (0*numbitsinchan)) <=NDATA;

          ODATA( (4*numbitsinchan-1) downto (3*numbitsinchan)) <= NDATA;
          ODATA( (3*numbitsinchan)-1 downto (2*numbitsinchan)) <= PDATA;
          ODATA( (2*numbitsinchan)-1 downto (1*numbitsinchan)) <=N_temp_reg;      
          ODATA( (1*numbitsinchan)-1 downto (0*numbitsinchan)) <=P_temp_reg;
          
          PAR_ERROR<= parP_odd_err or parN_odd_err or parP_odd_err_reg or parN_odd_err_reg;
        end if;
        
      end if;
    end if;
  end process;

  
  
end Behavioral;