BCID_counter.vhd

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


library work;
use work.CMXpackage.all;
use work.CMX_VME_defs.all;


-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity BCID_counter is
  port (
    reset          : in  std_logic;
    clk_40         : in  std_logic;
    BCID_out       : out std_logic_vector(11 downto 0);
    --VME control:
    ncs           : in    std_logic;    --ports forwarded to the vme register instances
    rd_nwr        : in    std_logic;
    ds            : in    std_logic;
    addr_vme      : in    std_logic_vector (15 downto 0);
    data_vme_in   : in    std_logic_vector (15 downto 0);
    data_vme_out  : out   std_logic_vector (15 downto 0);
    bus_drive     : out   std_logic
    );
end BCID_counter;

architecture Behavioral of BCID_counter is
  signal BCID_next : unsigned(11 downto 0);
  signal BCID_reg : unsigned(11 downto 0);
  signal BCID_reset_val : unsigned(11 downto 0);

  component vme_local_switch is
    port (
      data_vme_up          : out std_logic_vector (15 downto 0);
      data_vme_from_below  : in  arr_16;
      bus_drive_up         : out std_logic;
      bus_drive_from_below : in  std_logic_vector);
  end component vme_local_switch;
  
  component vme_inreg_notri_async is
    generic (
      ia_vme : integer;
      width  : integer);
    port (
      ncs           : in  std_logic;
      rd_nwr        : in  std_logic;
      ds            : in  std_logic;
      addr_vme      : in  std_logic_vector (15 downto 0);
      data_vme_in   : in  std_logic_vector (15 downto 0);
      data_vme_out  : out std_logic_vector (15 downto 0);
      bus_drive     : out std_logic;
      data_from_vme : out std_logic_vector (width-1 downto 0);
      data_to_vme   : in  std_logic_vector (width-1 downto 0));
  end component vme_inreg_notri_async;

  component vme_outreg_notri_async is
    generic (
      ia_vme : integer;
      width  : integer);
    port (
      ncs         : in  std_logic;
      rd_nwr      : in  std_logic;
      ds          : in  std_logic;
      addr_vme    : in  std_logic_vector (15 downto 0);
      data_vme    : out std_logic_vector (15 downto 0);
      bus_drive   : out std_logic;
      data_to_vme : in  std_logic_vector (width-1 downto 0));
  end component vme_outreg_notri_async;

  signal data_vme_out_local : arr_16(2 downto 0);
  signal bus_drive_local : std_logic_vector(2 downto 0);

  signal data_from_vme_REG_RW_BCID_RESET_VAL: std_logic_vector(15 downto 0);
  signal   data_to_vme_REG_RW_BCID_RESET_VAL: std_logic_vector(15 downto 0);

  signal data_from_vme_REG_RW_BC_RESET_ERROR_COUNTER_RESET : std_logic_vector(15 downto 0);
  signal   data_to_vme_REG_RW_BC_RESET_ERROR_COUNTER_RESET : std_logic_vector(15 downto 0);
  

  signal bc_reset_error_counter : unsigned(15 downto 0);

  signal error_counter_reset : std_logic; 
  
begin

  
  vme_local_switch_inst: entity work.vme_local_switch
    port map (
      data_vme_up           => data_vme_out,
      data_vme_from_below   => data_vme_out_local,
      bus_drive_up          => bus_drive,
      bus_drive_from_below  => bus_drive_local);

  
  vme_inreg_async_REG_RW_BCID_RESET_VAL: entity work.vme_inreg_notri_async
    generic map (
      ia_vme  => ADDR_REG_RW_BCID_RESET_VAL ,
      width   => 16)
    port map (
      ncs            => ncs,
      rd_nwr         => rd_nwr,
      ds             => ds,
      addr_vme       => addr_vme,
      data_vme_in    => data_vme_in,
      data_vme_out   => data_vme_out_local(0),
      bus_drive      => bus_drive_local (0),
      data_from_vme  => data_from_vme_REG_RW_BCID_RESET_VAL,
      data_to_vme    => data_to_vme_REG_RW_BCID_RESET_VAL);

  data_to_vme_REG_RW_BCID_RESET_VAL<=data_from_vme_REG_RW_BCID_RESET_VAL;
  BCID_reset_val<=unsigned(data_from_vme_REG_RW_BCID_RESET_VAL(11 downto 0));


  vme_outreg_notri_async_REG_RO_BC_RESET_ERROR_COUNTER: entity work.vme_outreg_notri_async
    generic map (
      ia_vme  => ADDR_REG_RO_BC_RESET_ERROR_COUNTER ,
      width   => 16)
    port map (
      ncs          => ncs,
      rd_nwr       => rd_nwr,
      ds           => ds,
      addr_vme     => addr_vme,
      data_vme     => data_vme_out_local (1),
      bus_drive    => bus_drive_local (1),
      data_to_vme  => std_logic_vector(bc_reset_error_counter));


  vme_inreg_async_REG_RW_BC_RESET_ERROR_COUNTER_RESET: entity work.vme_inreg_notri_async
    generic map (
      ia_vme  => ADDR_REG_RW_BC_RESET_ERROR_COUNTER_RESET,
      width   => 16)
    port map (
      ncs            => ncs,
      rd_nwr         => rd_nwr,
      ds             => ds,
      addr_vme       => addr_vme,
      data_vme_in    => data_vme_in,
      data_vme_out   => data_vme_out_local(2),
      bus_drive      => bus_drive_local (2),
      data_from_vme  => data_from_vme_REG_RW_BC_RESET_ERROR_COUNTER_RESET,
      data_to_vme    => data_to_vme_REG_RW_BC_RESET_ERROR_COUNTER_RESET);

  data_to_vme_REG_RW_BC_RESET_ERROR_COUNTER_RESET<=data_from_vme_REG_RW_BC_RESET_ERROR_COUNTER_RESET;
  error_counter_reset<=data_from_vme_REG_RW_BC_RESET_ERROR_COUNTER_RESET(0);
  
  BCID_next<=BCID_reg+1 when BCID_reg/=to_unsigned(3563,12) else to_unsigned(0,12); 
  --orbit has 3564 bunches

  process(clk_40)
  begin
    if rising_edge(clk_40) then
      if reset = '1' then
        if BCID_next/=BCID_reset_val then
          if bc_reset_error_counter/=to_unsigned(16#FFFF#,16) then
            bc_reset_error_counter<=bc_reset_error_counter+1;
          else
            bc_reset_error_counter<=to_unsigned(16#FFFF#,16);
          end if;
        end if;
        
        BCID_reg<=BCID_reset_val;
        
      else
        
        BCID_reg<=BCID_next;

        if error_counter_reset='1' then
          bc_reset_error_counter<=to_unsigned(0,16);
        end if;
        
      end if;
    end if;
  end process;

  BCID_out<=std_logic_vector(BCID_reg);
  
end Behavioral;