vme_inreg_rtl_notri_async.vhd

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LIBRARY ieee ;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;

-- YE: All files are loaded in the library "work"
-- LIBRARY cmm_main;          -- YE: this is a library, where package "vme_cmm" located
-- USE cmm_main.vme_cmm.all;  -- YE: package "vme_cmm" moved to the library "work"
use work.CMXpackage.all;      -- YE: so use package "vme_cmm" from library "work" (cmx_vat.vhd)
use work.CMX_VME_defs.all;

entity vme_inreg_notri_async is
  generic( 
    ia_vme : integer := 0;
    width  : integer := 16
    );
  port(
    
    ncs      : in     std_logic;
    rd_nwr   : in     std_logic;
    ds       : in     std_logic;

    addr_vme : in     std_logic_vector (15 downto 0);
    data_vme_in  : in  std_logic_vector (15 downto 0);
    data_vme_out : out std_logic_vector (15 downto 0);
    bus_drive : out std_logic;
    
    data_from_vme        : out std_logic_vector (width-1 downto 0);
    data_to_vme          :in std_logic_vector (width-1 downto 0)
    
    );

-- Declarations

end vme_inreg_notri_async ;
--------------------------------------------------------------------------------
ARCHITECTURE rtl OF vme_inreg_notri_async IS
--------------------------------------------------------------------------------
-- VME register, all bits are inputs to board (q).
-- Variable width q, max 16.
--

  signal ren: std_logic; -- vme read enable

  signal wen: std_logic; -- vme write enable

  
--------------------------------------------------------------------------------
BEGIN


  ren <= vme_ren (ia_vme, addr_vme, ncs, rd_nwr);
  wen <= vme_wen (ia_vme, addr_vme, ncs, rd_nwr);

  data_vme_out(width-1 downto 0)<=data_to_vme when ren='1' else (others=>'0');
  gz: if width<16 generate
    data_vme_out(15 downto width)<=(others=>'0');
  end generate gz;
  bus_drive<=ren;
  

  
  

  vme_w_proc: process (wen, ds)
    -- write access
  begin                                 
    if(ds'event and ds = '1') then
      if (wen = '1') then
        data_from_vme <= data_vme_in(width-1 downto 0);
      end if;
    end if;
  end process;
  


END rtl;