10 USE ieee.std_logic_1164.
all;
46 --------------------------------------------------------------------------------
48 --------------------------------------------------------------------------------
49 -- VME register, all bits are inputs to board (q).
50 -- Variable width q, max 16.
53 signal ren: ;
-- vme read enable
59 signal wen: ;
-- vme write enable
70 -- doesn't have to be held after
81 --component chipscope_icon_c1
83 -- CONTROL0 : inout std_logic_vector(35 downto 0));
86 --component chipscope_ila_inside_inreg
88 -- CONTROL : inout std_logic_vector(35 downto 0);
89 -- CLK : in std_logic;
90 -- DATA : in std_logic_vector(39 downto 0);
91 -- TRIG0 : in std_logic_vector(3 downto 0));
94 --signal CONTROL : std_logic_vector(35 downto 0);
95 --signal DATA_chipscope : std_logic_vector(39 downto 0);
96 --signal TRIG0_chipscope : std_logic_vector(3 downto 0);
98 --------------------------------------------------------------------------------
106 gz: if width<16 generate
113 -- detect a read enable stable and ds edge after and generate a pulse on read_detect signal
114 -- detect a write enable stable and ds edge and generate a pulse on
115 -- write_detect and update output (data_from_vme)
116 -- signal and update the output
118 begin -- process read_detect_proc
119 if rising_edge(clk) then -- rising clock edge
121 --detect rising edge, make sure signals are stable
130 --there is also a strobe after the read
138 --buffer the ren in a shift register
147 --buffer the wen and ds in shift register
173 gen_read_detect_delay: for i_del in 1 to VME_read_det_delay-1 generate
176 if rising_edge(clk) then
180 end generate gen_read_detect_delay;
186 --chipscope_icon_c1_inst: chipscope_icon_c1
188 -- CONTROL0 => CONTROL);
190 --chipscope_ila_inside_inreg_inst: chipscope_ila_inside_inreg
192 -- CONTROL => CONTROL,
194 -- DATA => DATA_chipscope,
195 -- TRIG0 => TRIG0_chipscope);
198 --TRIG0_chipscope(0)<=ds;
199 --TRIG0_chipscope(1)<=rd_nwr;
200 --TRIG0_chipscope(2)<=ren;
201 --TRIG0_chipscope(3)<=wen;
204 --DATA_chipscope(0)<=ds;
205 --DATA_chipscope(1)<=rd_nwr;
206 --DATA_chipscope(2)<=ren;
207 --DATA_chipscope(3)<=wen;
208 --DATA_chipscope(4)<=read_detect_sig;
209 --DATA_chipscope(5)<=write_detect_sig;
210 --DATA_chipscope(6) <=ds_r;
211 --DATA_chipscope(7) <=ds_rr;
212 --DATA_chipscope(8) <=ds_rrr;
213 --DATA_chipscope(9) <=ds_rrrr;
214 --DATA_chipscope(10)<=ds_rrrrr;
215 --DATA_chipscope(11)<=ds_rrrrrr;
216 --DATA_chipscope(12)<=ren_r;
217 --DATA_chipscope(13)<=ren_rr;
218 --DATA_chipscope(14)<=ren_rrr;
219 --DATA_chipscope(15)<=ren_rrrr;
220 --DATA_chipscope(16)<=ren_rrrrr;
221 --DATA_chipscope(17)<=ren_rrrrrr;
222 --DATA_chipscope(18)<=wen_r;
223 --DATA_chipscope(19)<=wen_rr;
224 --DATA_chipscope(20)<=wen_rrr;
225 --DATA_chipscope(21)<=wen_rrrr;
226 --DATA_chipscope(22)<=wen_rrrrr;
227 --DATA_chipscope(23)<=wen_rrrrrr;
228 --DATA_chipscope(39 downto 24)<=addr_vme;
231 -- vme_w_proc: process (iq, wen, ds)
234 -- if(ds'event and ds = '1') then
235 -- if (wen = '1') then
236 -- iq <= data_vme(width-1 downto 0);
std_logic_vector (15 downto 0) data_vme_rrrr
out data_vme_outstd_logic_vector (15 downto 0)
out data_from_vmestd_logic_vector (width - 1 downto 0)
std_logic read_detect_sig
read_write_detect_procclk
out write_detectstd_logic
std_logic write_detect_sig
std_logic_vector (15 downto 0) data_vme_rrr
std_logic_vector (VME_read_det_delay - 1 downto 0) read_detect_delay_line
in addr_vmestd_logic_vector (15 downto 0)
in data_to_vmestd_logic_vector (width - 1 downto 0)
std_logic_vector (15 downto 0) data_vme_r
in data_vme_instd_logic_vector (15 downto 0)
std_logic_vector (15 downto 0) data_vme_rr