vme_inreg_rtl.vhd

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LIBRARY ieee ;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;

-- YE: All files are loaded in the library "work"
-- LIBRARY cmm_main;          -- YE: this is a library, where package "vme_cmm" located
-- USE cmm_main.vme_cmm.all;  -- YE: package "vme_cmm" moved to the library "work"
use work.CMXpackage.all;      -- YE: so use package "vme_cmm" from library "work" (cmx_vat.vhd)
use work.CMX_VME_defs.all;

entity vme_inreg is
  generic( 
    ia_vme : integer := 0;
    width  : integer := 16
    );
  port(
    clk : in std_logic;

    ncs      : in     std_logic;
    rd_nwr   : in     std_logic;
    ds       : in     std_logic;

    addr_vme : in     std_logic_vector (15 downto 0);
    data_vme : inout  std_logic_vector (15 downto 0);

    
    data_from_vme        : out std_logic_vector (width-1 downto 0);
    data_to_vme          :in std_logic_vector (width-1 downto 0);
    
    read_detect : out std_logic;
    write_detect : out std_logic
    );

-- Declarations

end vme_inreg ;
--------------------------------------------------------------------------------
ARCHITECTURE rtl OF vme_inreg IS
--------------------------------------------------------------------------------
-- VME register, all bits are inputs to board (q).
-- Variable width q, max 16.
--

  signal ren: std_logic; -- vme read enable
  signal ren_r,ren_rr,ren_rrr,ren_rrrr,ren_rrrrr,ren_rrrrrr: std_logic; --above
                                                                        --registered to
                                                                        --sys clk


  signal wen: std_logic; -- vme write enable
  signal wen_r,wen_rr,wen_rrr,wen_rrrr,wen_rrrrr,wen_rrrrrr: std_logic; --above
                                                                        --registered to
                                                                        --sys clk


  signal ds_r,ds_rr,ds_rrr,ds_rrrr,ds_rrrrr,ds_rrrrrr,ds_rrrrrrr,ds_rrrrrrrr : std_logic; -- previous
                                                                   -- registered
                                                                   -- value of strobe

  signal data_vme_r,data_vme_rr,data_vme_rrr,data_vme_rrrr: std_logic_vector(15 downto 0);  -- registered value of data, it
                                               -- doesn't have to be held after
                                               -- ds


  signal read_detect_sig, write_detect_sig : std_logic;  --signals that pulse
                                                         --high on read or
                                                         --write op, forwarded
                                                         --to output

  signal read_detect_delay_line : std_logic_vector(VME_read_det_delay-1 downto 0);
  
  --component chipscope_icon_c1
  --  port (
  --    CONTROL0 : inout std_logic_vector(35 downto 0));
  --end component;
  --
  --component chipscope_ila_inside_inreg
  --  port (
  --    CONTROL : inout std_logic_vector(35 downto 0);
  --    CLK     : in    std_logic;
  --    DATA    : in    std_logic_vector(39 downto 0);
  --    TRIG0   : in    std_logic_vector(3 downto 0));
  --end component;
  --
  --signal CONTROL : std_logic_vector(35 downto 0);
  --signal DATA_chipscope    : std_logic_vector(39 downto 0);
  --signal TRIG0_chipscope   : std_logic_vector(3 downto 0);
  
--------------------------------------------------------------------------------
BEGIN


  ren <= vme_ren (ia_vme, addr_vme, ncs, rd_nwr);
  wen <= vme_wen (ia_vme, addr_vme, ncs, rd_nwr);


  --async mode to drive the bus/let go of the bus as soon as ren is updated
  vme_r_proc: process (ren, data_to_vme)
    -- read access
  begin
    data_vme <= "ZZZZZZZZZZZZZZZZ";
    if (ren = '1') then
      data_vme <= (others=>'0');
      data_vme(width-1 downto 0) <= data_to_vme(width-1 downto 0);
    end if;    
  end process; 

  
      
  -- detect a read enable stable and ds edge after and generate a pulse on read_detect signal
  -- detect a write enable stable and ds edge and generate a pulse on
  -- write_detect and update output (data_from_vme)
  -- signal and update the output
  read_write_detect_proc: process (clk)
  begin  -- process read_detect_proc
    if rising_edge(clk) then  -- rising clock edge

      --detect rising edge, make sure signals are stable
      if wen_rrrrrr='1' and wen_rrrrr='1' and wen_rrrr='1' and wen_rrr='1' and wen_rr='1' and wen_r='1'
        and ds_rrrrrrrr='0' and ds_rrrrrrr='0'  and ds_rrrrrr='0' and ds_rrrrr='1' and ds_rrrr='1'  and ds_rrr='1' then
        write_detect_sig <= '1';
        data_from_vme(width-1 downto 0) <= data_vme_rrrr(width-1 downto 0);
      else
        write_detect_sig <= '0';
      end if;

      --there is also a strobe after the read
      if ren_rrrrrr='1' and ren_rrrrr='1' and ren_rrrr='1' and ren_rrr='1' and ren_rr='1' and ren_r='1'
        and ds_rrrrrrrr='0' and ds_rrrrrrr='0'  and ds_rrrrrr='0' and ds_rrrrr='1' and ds_rrrr='1'  and ds_rrr='1' then
        read_detect_sig <= '1';
      else
        read_detect_sig <= '0';
      end if;

      --buffer the ren in a shift register
      
      ren_rrrrrr<=ren_rrrrr;
      ren_rrrrr<=ren_rrrr;
      ren_rrrr<=ren_rrr;
      ren_rrr<=ren_rr;
      ren_rr<=ren_r;
      ren_r<=ren;
    
      --buffer the wen and ds in shift register
      wen_rrrrrr<=wen_rrrrr;
      wen_rrrrr<=wen_rrrr;
      wen_rrrr<=wen_rrr;
      wen_rrr<=wen_rr;
      wen_rr<=wen_r;
      wen_r<=wen;

      ds_rrrrrrrr<=ds_rrrrrrr;
      ds_rrrrrrr<=ds_rrrrrr;
      ds_rrrrrr<=ds_rrrrr;
      ds_rrrrr<=ds_rrrr;
      ds_rrrr<=ds_rrr;
      ds_rrr<=ds_rr;
      ds_rr<=ds_r;
      ds_r<=ds;

      data_vme_rrrr<=data_vme_rrr;
      data_vme_rrr<=data_vme_rr;
      data_vme_rr<=data_vme_r;
      data_vme_r<=data_vme;
      
    end if;
  end process read_write_detect_proc;

  read_detect_delay_line(0)<=read_detect_sig;
  gen_read_detect_delay: for i_del in 1 to VME_read_det_delay-1 generate
    process(clk)
    begin
      if rising_edge(clk) then
        read_detect_delay_line(i_del)<=read_detect_delay_line(i_del-1);
      end if;
    end process;
  end generate gen_read_detect_delay;
  
  read_detect<=read_detect_delay_line(VME_read_det_delay-1);
  write_detect<=write_detect_sig;
  

  --chipscope_icon_c1_inst: chipscope_icon_c1
  --  port map (
  --    CONTROL0 => CONTROL);
  --
  --chipscope_ila_inside_inreg_inst: chipscope_ila_inside_inreg
  --  port map (
  --    CONTROL => CONTROL,
  --    CLK     => clk,
  --    DATA    => DATA_chipscope,
  --    TRIG0   => TRIG0_chipscope);
  --
  --
  --TRIG0_chipscope(0)<=ds;
  --TRIG0_chipscope(1)<=rd_nwr;
  --TRIG0_chipscope(2)<=ren;
  --TRIG0_chipscope(3)<=wen;
  --
  --
  --DATA_chipscope(0)<=ds;
  --DATA_chipscope(1)<=rd_nwr;
  --DATA_chipscope(2)<=ren;
  --DATA_chipscope(3)<=wen;
  --DATA_chipscope(4)<=read_detect_sig;
  --DATA_chipscope(5)<=write_detect_sig;
  --DATA_chipscope(6) <=ds_r; 
  --DATA_chipscope(7) <=ds_rr; 
  --DATA_chipscope(8) <=ds_rrr; 
  --DATA_chipscope(9) <=ds_rrrr; 
  --DATA_chipscope(10)<=ds_rrrrr; 
  --DATA_chipscope(11)<=ds_rrrrrr; 
  --DATA_chipscope(12)<=ren_r;      
  --DATA_chipscope(13)<=ren_rr;     
  --DATA_chipscope(14)<=ren_rrr;    
  --DATA_chipscope(15)<=ren_rrrr;   
  --DATA_chipscope(16)<=ren_rrrrr;  
  --DATA_chipscope(17)<=ren_rrrrrr; 
  --DATA_chipscope(18)<=wen_r;      
  --DATA_chipscope(19)<=wen_rr;     
  --DATA_chipscope(20)<=wen_rrr;    
  --DATA_chipscope(21)<=wen_rrrr;   
  --DATA_chipscope(22)<=wen_rrrrr;  
  --DATA_chipscope(23)<=wen_rrrrrr; 
  --DATA_chipscope(39 downto 24)<=addr_vme;
  --                     
--
--  vme_w_proc: process (iq, wen, ds)
--    -- write access
--  begin                                   
--    if(ds'event and ds = '1') then
--      if (wen = '1') then
--        iq <= data_vme(width-1 downto 0);
--      end if;
--    end if;
--  end process;
  


END rtl;