vme_outreg_rtl_notri_async.vhd

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LIBRARY ieee ;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;


use work.CMXpackage.all;
use work.CMX_VME_defs.all;

entity vme_outreg_notri_async is
  generic( 
    ia_vme : integer := 0;
    width  : integer := 16
    );
  port(
    ncs      : in     std_logic;
    rd_nwr   : in     std_logic;
    ds       : in     std_logic;

    addr_vme : in     std_logic_vector (15 downto 0);
    data_vme : out    std_logic_vector (15 downto 0);
    bus_drive : out std_logic;
    
    data_to_vme  : in     std_logic_vector (width-1 downto 0)
    );

-- Declarations

end vme_outreg_notri_async ;
--------------------------------------------------------------------------------
ARCHITECTURE rtl OF vme_outreg_notri_async IS
--------------------------------------------------------------------------------
-- VME register, all bits are inputs to board (q).
-- Variable width q, max 16.
--

  signal ren: std_logic; -- vme read enable
  
  
--------------------------------------------------------------------------------
BEGIN


  ren <= vme_ren (ia_vme, addr_vme, ncs, rd_nwr);

  data_vme(width-1 downto 0)<=data_to_vme when ren='1' else (others=>'0');
  gz: if width<16 generate
    data_vme(15 downto width)<=(others=>'0');
  end generate gz;
  bus_drive<=ren;
  
  
END rtl;