7 USE ieee.std_logic_1164.
all;
8 USE ieee.numeric_std.
all;
36 end vme_outreg_notri ;
37 --------------------------------------------------------------------------------
39 --------------------------------------------------------------------------------
40 -- VME register, all bits are inputs to board (q).
41 -- Variable width q, max 16.
44 signal ren: ;
-- vme read enable
58 --------------------------------------------------------------------------------
66 gz: if width<16 generate
71 -- detect a read enable edge and generate a pulse on read_detect signal
73 begin -- process read_detect_proc
74 if rising_edge(clk) then -- rising clock edge
103 gen_read_detect_delay: for i_del in 1 to VME_read_det_delay-1 generate
106 if rising_edge(clk) then
110 end generate gen_read_detect_delay;
std_logic read_detect_sig
out data_vmestd_logic_vector (15 downto 0)
std_logic_vector (VME_read_det_delay - 1 downto 0) read_detect_delay_line
in data_to_vmestd_logic_vector (width - 1 downto 0)
in addr_vmestd_logic_vector (15 downto 0)