and_all.vhd

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

library work;
use work.CMXpackage.all;


-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity and_all is
  generic
    (
      numbits    : integer    := 2 -- Set to 1 to speed up sim reset
      );
  port (
    DATA         : in  std_logic_vector(numbits - 1 downto 0);
    and_all       : out std_logic);
end and_all;

architecture Behavioral of and_all is
  signal tmp : std_logic_vector(numbits - 1 downto 0);  
  
begin

  tmp(0)<=DATA(0);
  and_gen: for bitnum in 1 to (numbits-1) generate
    tmp(bitnum) <= DATA(bitnum) and tmp(bitnum-1);
  end generate and_gen;
  and_all<=tmp(numbits-1);
  
end Behavioral;