adder_counter.vhd

Go to the documentation of this file.

library ieee;
use ieee.std_logic_1164.all;
use IEEE.NUMERIC_STD.ALL;
library unisim;
use unisim.vcomponents.all;

LIBRARY work;
use work.CMX_flavor_package.all;


entity adder_counter is
  generic(
    flavor         : T_SLV2    := "00";                                   -- JET/CPM/SUMET
    thresholds_num : integer   := 25;
    width          : integer   := 60
    ); 
  port( 
    clk            : T_SL;                                       -- clock
    reset          : T_SL;                                       -- reset  
    inhibit        : T_SL;                                       -- inhibit
    data           : in  std_logic_vector(width-1 downto 0);     -- data
    cnt_arr        : out cnt_mult_arr(thresholds_num-1 downto 0) -- counters 
    );

end adder_counter;

architecture Behavioral of adder_counter is

  component mult_cnt is
    generic(
      width      : integer := 3
      ); 
    port( 
      clk            : in  T_SL;                                -- clock
      reset          : in  T_SL;                                -- reset  
      inhibit        : in  T_SL;                                -- inhibit
      data           : in  std_logic_vector(width-1 downto 0);  -- data
      cnt_out        : out T_SLV32                              -- mult
      );

  end component;


begin

-- ------------------------------------------------------------------------------------
--                                 JETS MULTIPLICITY COUNTERS 
-- ------------------------------------------------------------------------------------
  gen_jet_mult_cnt: if flavor = "00" generate        -- jets


    cnt_mult_a: for i in 0 to thresholds_num-16 generate

      cnt_mult_a_i: mult_cnt 
        generic map(
          width       => 3
          )
        port map( 
          clk         => clk,                           -- clock
          reset       => reset,                         -- reset  
          inhibit     => inhibit ,                       -- inhibit
          data        => data((3*i)+2 downto 3*i),      -- data
          cnt_out     => cnt_arr (i)                     -- mult
          );

    end generate cnt_mult_a;

    cnt_mult_b: for i in 0 to thresholds_num-11 generate

      cnt_mult_b_i: mult_cnt 
        generic map(
          width       => 2
          ) 
        port map( 
          clk         => clk,                                -- clock
          reset       => reset,                              -- reset  
          inhibit     => inhibit ,                            -- inhibit
          data        => data(((2*i)+1)+30 downto (2*i)+30), -- data
          cnt_out     => cnt_arr (i+10)                       -- mult
          );

    end generate cnt_mult_b;

  end generate gen_jet_mult_cnt;


-- ------------------------------------------------------------------------------------
--                                 CPMs MULTIPLICITY COUNTERS 
-- ------------------------------------------------------------------------------------

  gen_cpm_mult_cnt: if flavor = "01" generate        -- cpm


    cnt_mult: for i in 0 to thresholds_num-1 generate

      cnt_mult_i: entity work.mult_cnt 
        generic map(
          width       => 3
          ) 
        port map( 
          clk         => clk,                           -- clock
          reset       => reset,                         -- reset  
          inhibit     => inhibit ,                       -- inhibit
          data        => data((3*i)+2 downto 3*i),      -- data
          cnt_out     => cnt_arr (i)                     -- mult
          );

    end generate cnt_mult;

  end generate gen_cpm_mult_cnt;



-- ------------------------------------------------------------------------------------
--                                 SUMEt COUNTERS 
-- ------------------------------------------------------------------------------------

  gen_sumEt_cnt: if flavor = "10" generate        -- sumEt


    cnt_sumEt: for i in 0 to thresholds_num-1 generate

      cnt_sumEt_i: entity work.mult_cnt 
        generic map(
          width       => 1
          ) 
        port map( 
          clk         => clk,                           -- clock
          reset       => reset,                         -- reset  
          inhibit     => inhibit ,                       -- inhibit
          data        => data(i downto i),              -- data
          cnt_out     => cnt_arr (i)                     -- mult
          );

    end generate cnt_sumEt;

  end generate gen_sumEt_cnt;


end Behavioral;