mult_cnt.vhd

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library ieee;
use ieee.std_logic_1164.all;
use IEEE.NUMERIC_STD.ALL;
library unisim;
use unisim.vcomponents.all;
LIBRARY work;
use work.CMX_flavor_package.all;


entity mult_cnt is
  generic(
    width      : integer := 3
    ); 
  port( 
    clk            : in  T_SL;                                -- clock
    reset          : in  T_SL;                                -- reset  
    inhibit        : in  T_SL;                                -- inhibit
    data           : in  std_logic_vector(width-1 downto 0);  -- data
    cnt_out        : out T_SLV32                              -- mult
    );

end mult_cnt;

architecture Behavioral of mult_cnt is

  signal cnt : std_logic_vector(32 downto 0);

  signal inhibit_r_local, reset_r_local : std_logic;
  
begin

  process(clk)
  begin
    if rising_edge(clk) then
      inhibit_r_local<=inhibit;
      reset_r_local<=reset;
    end if;
  end process;
  
  process(clk)
  begin 
    if clk'event and clk = '1' then  -- raising clock edge
      
      if reset_r_local = '1' then
        cnt <= (others=>'0');
      else
        if inhibit_r_local = '0' then
          if cnt(32) = '1' then
            cnt <=  (others=>'1');
          else
            cnt <=  std_logic_vector(unsigned(cnt) + unsigned(data));
          end if;           
        end if;
      end if; 
      
      cnt_out <= cnt(31 downto 0); 
      
    end if;  
  end process;

end Behavioral;