mini_fifo_synchroniser.vhd

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

library work;
use work.CMXpackage.all;


-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
-- use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity mini_fifo_synchroniser is
    port (
    set_mem_ctr_i_out    : out  std_logic;
    set_mem_ctr_o_out    : out  std_logic;
    clk_i_dom   : in std_logic;          --input domain clock
    clk_o_dom   : in std_logic;          --output domain clock
    set         : in std_logic);          --set signal (active high)
end mini_fifo_synchroniser;

architecture Behavioral of mini_fifo_synchroniser is

  attribute keep : string; 

  signal set_r_clk_i : std_logic;
  signal set_rr_clk_i : std_logic;
  

  
  signal set_rr_clk_i_r_clk_o : std_logic;
  
  signal set_mem_ctr_i : std_logic;
  signal set_mem_ctr_o : std_logic;

  attribute keep of set_r_clk_i, set_rr_clk_i, set_mem_ctr_i, set_rr_clk_i_r_clk_o, set_mem_ctr_o : signal is "TRUE";

  
begin


  i_ctr_proc: process (clk_i_dom)
  begin  -- process i_ctr_proc
    if rising_edge(clk_i_dom) then
      set_mem_ctr_i<=set_rr_clk_i;
      set_rr_clk_i<=set_r_clk_i;
      set_r_clk_i<=set;
    end if;
  end process i_ctr_proc;

  o_ctr_proc: process (clk_o_dom)
  begin  -- process i_ctr_proc
    if rising_edge(clk_o_dom) then

      set_mem_ctr_o <=  set_rr_clk_i_r_clk_o;
      set_rr_clk_i_r_clk_o <= set_rr_clk_i;
    end if;
  end process o_ctr_proc;

  set_mem_ctr_o_out<=set_mem_ctr_o;
  set_mem_ctr_i_out<=set_mem_ctr_i;
  
  
end Behavioral;