mini_fifo_synchroniser.vhd File Reference

this modules provides synchronisers for the mini fifos that transfer the data into the GTX TX Clock domains More...

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Entities
mini_fifo_synchroniser	entity
Behavioral	architecture

Detailed Description

this modules provides synchronisers for the mini fifos that transfer the data into the GTX TX Clock domains

Author

W. Fedorko

Date

30 Apr 2013

The 'set' (active high) signal can come from any domain but is assumed to be synchronised to the output clock domain. It is then piped through synchroniser first in the input clock domain and then in the output clock domain (and also delayed by the same amount in the input clock domain. Data starts flowing through the fifo 4 ticks of the input clock after de-assertion of the set signal and appears on the output the next-to-following output clock tick Mod: the synchronisation is now done by an outside synchroniser so that there is only one synchroniser for the whole group

Dependencies: CoreGen wrapper for a Block Ram

Revision: Revision 0.01 - File Created Additional Comments:

Definition in file mini_fifo_synchroniser.vhd.