mini_fifo.vhd

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

library work;
use work.CMXpackage.all;


-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity mini_fifo is
  generic
    (
      numbits    : integer    := TX_fifo_indata_length 
      );
  port (
    DATA_in     : in  std_logic_vector(numbits-1 downto 0);
    DATA_out    : out  std_logic_vector(numbits-1 downto 0);
    clk_i_dom   : in std_logic;          --input domain clock
    clk_o_dom   : in std_logic;          --output domain clock
    set_mem_ctr_i   : in std_logic;
    set_mem_ctr_o   : in std_logic);          --set signal (active high) 
                                              --(after sync to respective domains)
end mini_fifo;

architecture Behavioral of mini_fifo is

--  signal set_r_clk_i : std_logic;
--  signal set_rr_clk_i : std_logic;
--  signal set_rrr_clk_i : std_logic;

  
--  signal set_rr_clk_i_r_clk_o : std_logic;


  signal set_mem_ctr_i_r,set_mem_ctr_o_r : std_logic;  -- the set signal
                                                       -- registered once to
                                                       -- help timing closure
                                                       -- in respective clock domains

  signal ctr_i : unsigned(2 downto 0);  --input side counter
  signal ctr_o : unsigned(2 downto 0);  --output side counter
  signal ctr_i_next : unsigned(2 downto 0);  --input side counter
  signal ctr_o_next : unsigned(2 downto 0);  --output side counter


  
  signal ena   : STD_LOGIC;
  signal wea   : STD_LOGIC_VECTOR(0 DOWNTO 0);
  signal addra : STD_LOGIC_VECTOR(2 DOWNTO 0);
  signal dina  : STD_LOGIC_VECTOR(numbits-1 DOWNTO 0);

  signal doutb  : STD_LOGIC_VECTOR(numbits-1 DOWNTO 0);
  
  signal rstb  : STD_LOGIC;
  signal enb   : STD_LOGIC;
  signal addrb : STD_LOGIC_VECTOR(2 DOWNTO 0);

  
  component block_mem
    port (
      clka  : IN  STD_LOGIC;
      ena   : IN  STD_LOGIC;
      wea   : IN  STD_LOGIC_VECTOR(0 DOWNTO 0);
      addra : IN  STD_LOGIC_VECTOR(2 DOWNTO 0);
      dina  : IN  STD_LOGIC_VECTOR(numbits-1 DOWNTO 0);
      clkb  : IN  STD_LOGIC;
      rstb  : IN  STD_LOGIC;
      enb   : IN  STD_LOGIC;
      addrb : IN  STD_LOGIC_VECTOR(2 DOWNTO 0);
      doutb : OUT STD_LOGIC_VECTOR(numbits-1 DOWNTO 0));
  end component;
  
begin

  
  set_mem_ctr_i_del_proc : process (clk_i_dom)
  begin
    if rising_edge(clk_i_dom) then
      set_mem_ctr_i_r<=set_mem_ctr_i;
    end if;
  end process set_mem_ctr_i_del_proc;

  
  set_mem_ctr_o_del_proc : process (clk_o_dom)
  begin
    if rising_edge(clk_o_dom) then
      set_mem_ctr_o_r<=set_mem_ctr_o;
    end if;
  end process set_mem_ctr_o_del_proc;

  
  i_ctr_proc: process (clk_i_dom)
  begin  -- process i_ctr_proc
    if rising_edge(clk_i_dom) then

      if set_mem_ctr_i_r='0' then
        ctr_i<=ctr_i_next;
      else
        ctr_i<=to_unsigned(0,3);
      end if;
    end if;
    
  end process i_ctr_proc;

  o_ctr_proc: process (clk_o_dom)
  begin  -- process i_ctr_proc
    if rising_edge(clk_o_dom) then

      

      DATA_out<=doutb;                  --this register needed - otherwise the
                                        --thing does not meet timing

      if set_mem_ctr_o_r='0' then
        ctr_o<=ctr_o_next;
      else
        ctr_o<=to_unsigned(6,3);
      end if;
    end if;
  end process o_ctr_proc;

  ctr_o_next <= ctr_o+1;
  ctr_i_next <= ctr_i+1;
  
  wea(0)<=not set_mem_ctr_i_r;
  ena <= not set_mem_ctr_i_r;
  addra <= std_logic_vector(ctr_i);

  --dina<=DATA_in when ena='1' else (others => '0');
  dina<=DATA_in;
  
  addrb <=  std_logic_vector(ctr_o);
  rstb <= set_mem_ctr_o_r;
  enb <= not set_mem_ctr_o_r;
  

  block_mem_i: block_mem
    port map (
      clka   => clk_i_dom,
      ena    => ena,
      wea    => wea,
      addra  => addra,
      dina   => dina,
      clkb   => clk_o_dom,
      rstb   => rstb,
      enb    => enb,
      addrb  => addrb,
      doutb  => doutb);
  
 
end Behavioral;